SigmaStudio+ is used in dual-core mode

Hi,

Could you please share your schematic for analyzing this issue.

Thanks

Hi Chiru & Sakthivel,

Any updates for this issue?

Our schematics were so complex that one core could not run well enough. We urgently needed to use 21593's dual core. Please give us useful help, thank you.

Hi Jonny,
We will check and get back to you, since your schematic having 48 Input/40 Output channels we need to make some modifications to the schematic to test on evaluation boards.

whether your simple schematic worked with 48 Input/40 Output channels configuration? 
Is my understanding correct that you are facing issue only when using complex schematic with more modules?
Any idea what your schematic MIPS is?
Since your schematic block size is set to 16 there could be a possibility for MIPS overshoot when running with 48 Input/40 Output channels.     

Hi Sakthivel,

1. The schematic of attachment can work normally

2, I checked the MIPS and it didn't overshoot 

3, Our project has 48 input  & 40 output channel. In my test on EV board only 16 input /16 output channel is actually used. The attachment has the related configuration of Sport port, and the unused channel is not connected to the data input/output port through SRU

4. Because there are too many input and output channels, if the block size is set to 64, it will consume more memory, so I try to set it to 32 and 16

5, The audio process is as follows:

Core1 Sport In (48CH) -> Core1 SS+ -> Out to Core2 (40CH) -> Core2 In(40CH) - >  Core2 SS+ -> Out to Core1(40CH) -> Core1 Sport Out(40CH)

Attached is my test schematic and part of the source code for your reference.

6354.Test.zip

Hi Sakthivel,

1. The schematic of attachment can work normally

2, I checked the MIPS and it didn't overshoot 

3, Our project has 48 input  & 40 output channel. In my test on EV board only 16 input /16 output channel is actually used. The attachment has the related configuration of Sport port, and the unused channel is not connected to the data input/output port through SRU

4. Because there are too many input and output channels, if the block size is set to 64, it will consume more memory, so I try to set it to 32 and 16

5, The audio process is as follows:

Core1 Sport In (48CH) -> Core1 SS+ -> Out to Core2 (40CH) -> Core2 In(40CH) - >  Core2 SS+ -> Out to Core1(40CH) -> Core1 Sport Out(40CH)

Attached is my test schematic and part of the source code for your reference.

6354.Test.zip