Post Go back to editing

Help with Running DemoUc application with custom schematic

Category: Software
Software Version: CCES


I'm working my way through the document - SIGMASTUDIO FOR SHARC (ADSP-SC5XX/ADSP-215XX) - QUICK START GUIDE

I am using the EZKIT-SC573 board

CCES  product version - IDE version 2.11.113

I have got to section 7 - DemoUc application and can run the program successfully using the pre built DXEs that are in the release build.

If i clean and rebuild all the cores and attempt to run i get an error.

in Core 1

ASSERT [eRet == ADI_SS_FW_SUCCESS] fails at "C:\Analog Devices\SoftwareModules\SigmaStudioForSHARC-SH-Rel4.7.0\Target\Examples\DemoUc\ADSP-SC57x\Source\adi_ss_uc_app_sh0.c":137

which is 

eRet = adi_ss_fw_Init(pAppSharcCore0Info->hssFWHandle, &pAppSharcCore0Info->oFWConfig);
if (eRet != ADI_SS_FW_SUCCESS)
pAppSharcCore0Info->nApplicationStatus |= ADI_SS_FW_INIT_FAILED;

after doing a bit more debugging i found the error that caused the assert to be triggered which is in the function 'FWAlgo_Init' in adi_ss_fw_internal.c

the function call  at line 462  'adi_ss_create' returns with E_ADI_SS_INSUFFICIENT_MEMORY

/* SSn creation */
eSSnRes = adi_ss_create(&pAlgoInfo->handle, pMemMap);

i would like to figure this out as if i go to the next section and run DemoUc with a custom schematic and then i have to rebuild the project i  expect it to fail.

i tried changing the value assigned to ADI_SS_CONTROL_FW_ARM_MEMORY but that didn't work. i also checked i was putting in a big enough value by checking the size of the tSSARMFWInfo structure.

i also increased the memory allocated to in adi_ss_fw_config.h and adi_ss_fw_config_2156.h

#define ADI_SS_SHARC_FW_MEMORY                          (12832U) //(6272U)
#define ADI_SS_CONTROL_FW_SHARC_MEMORY      (15576U) //(11948U)

i'm at a bit of a loss now as not sure what  'adi_ss_create' is doing 

anyone else had a problem with this  or have i missed something or doing something i shouldn't

any help appreciated, thanks

Parents Reply
  • Hi Sakthivel P,

    Thank you very much for the information. using that process i managed to build and run the project. 

    I would just like to understand the process a lot better and i think i'm not understanding something.

    I was just a bit confused on item 10.

    "Repeat the steps 2 to 9 once again, which is required to match the memory allocation done with the newly generated schematic source.
    Please note, the repeating source file generation should be followed every time if there is a change in target application or SigmaStudio schematic application"

    If i change the sigmastudio schematic, then that in turn changes the target application which means i need to update the Sigma studio as the DXE will change....will i be just in an endless loop ? at what point do i stop looping ?

    Thank you for any help