Dear,
We using Sigmastudio 4.5 for sharc and crosscore 2.9.4
There is probably an incorrect clock divider calculation for the PCG in sigmastudio framework.
See : PCG_Init() in 'adi_ss_fw_pcg.c'
When the option 'ADI_SS_FW_PCG_DISABLE_EXT_CLK' is used for the clock source the CLKIN_0 or CLKIN_1, normally 25MHz are the source clocks and not 24.576MHz.
/* Clock divided for required bit clock */ nClkDivider = ((pPCGConfig->nEnExtInputClk == 0U) ? (ADI_SS_FW_PCG_EXT_CLKIN_FREQ_24576000HZ / nBlk0) : (pPCGConfig->nExtClk / nBlk0));
To resolve this issue the code should be replaced by:
..... uint32_t nClkIn; ...... switch (ePCGDevice) { case ADI_SS_FW_PCG_A: case ADI_SS_FW_PCG_B: nClkIn = CLKIN0; break; case ADI_SS_FW_PCG_C: case ADI_SS_FW_PCG_D: nClkIn = CLKIN1; break; default: return (ADI_SS_FW_PCG_FAILED); } /* Clock divided for required bit clock */ nClkDivider = ((pPCGConfig->nEnExtInputClk == 0U) ? (nClkIn / nBlk0) : (pPCGConfig->nExtClk / nBlk0));
In 'adi_ss_hal.h' replace the follow code:
#define CLKIN 25000000 ==> remove this file and add the next 2 defines #define CLKIN0 25000000 #define CLKIN1 25000000
Is this correct?