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add more SPORT to ucDemo for SC589 has run out of memory on L2 memory.


We using Sigmastudio 4.5 , Sigmastudio 4.5  for sharc and crosscore 2.9.4 on a sharc ADSP SC589.

When we add more sports to the ucDemo for SC589, we run out of memory on L2 memory.

We need 7 sports.

We had already try to change the following line in the .ld file.

/* ARM Core 0 L2 RAM, uncached */
/* MEM_L2_UNCACHED : ORIGIN = 0x20084000, LENGTH = 28K */
MEM_L2_UNCACHED : ORIGIN = 0x20084000, LENGTH = 76K /* max 77Kb */

/* ARM Core 0 L2 RAM, cached */
/* MEM_L2_CACHED : ORIGIN = 0x2008B000, LENGTH = 84K */
MEM_L2_CACHED : ORIGIN = 0x20097000, LENGTH = 32K /* max 35Kb */

After these changes we had the following overflow message.

..... `.ss_text' will not fit in region `MEM_L2_CACHED'
region `MEM_L2_CACHED' overflowed by 32684 bytes

What we need to change so that everything fits in the L2 memory.


  • Hi,
    You may need to adjust the L2 memory region in ARM and SHARC as well if your application cant fit in already allocated L2 cached and  un-cached memory. Please tryout the below steps,

    1. In ARM project "system - Linker - ss4s.ld" file adjust the un-chaned memory 

     MEM_L2_UNCACHED : ORIGIN = 0x20084000, LENGTH = 76K 

    2. Adjust the cached memory origin based on memory adjusted for "MEM_L2_UNCACHED " i.e.) 76K 

    MEM_L2_CACHED : ORIGIN = 0x20097000, LENGTH = 32K 

    3. If L2 cached not sufficient then adjust the required memory in MEM_L2_CORE2
     MEM_L2_CACHED : ORIGIN = 0x20097000, LENGTH = 64K 

    MEM_L2_CORE2 (r) : ORIGIN = 0x200A7000, LENGTH = 32K

    4. The "MMUConfig.c" in ARM project "system - MMU" should be adjusted for above L2 Memory adjustments as below,

      { 0x20084000u, 0x20096FFFu, ADI_MMU_RW_UNCACHED }, /* 76KB ARM uncached L2 */
    #if defined(__ADSPSC582__)
    { 0x20088000u, 0x200A3FFFu, ADI_MMU_WB_CACHED }, /* 112KB ARM cached L2 */
    { 0x200A4000u, 0x200BFFFFu, ADI_MMU_RW_UNCACHED }, /* 104KB SHARC0, & 8KB boot code working area */
    { 0x20097000u, 0x200A6FFFu, ADI_MMU_WB_CACHED }, /* 64KB ARM cached L2 */
    { 0x200A7000u, 0x200BFFFFu, ADI_MMU_RW_UNCACHED }, /* 88KB SHARC1, SHARC0, & 8KB boot code working area */

    5. The "app.ldf" in SHARC core projects "system - startup_ldf" should be adjusted, Since the SHARC L2 memory origin modified as below, 

       mem_L2B5B6_bw           { TYPE(BW RAM) START(0x200a7000) END(0x200affff) WIDTH(8) }

    Please let us know if you are facing any issue or further clarifications.


  • Dear,

    the following line must also be modified as follows:

       mem_L2B2toB4_bw         { TYPE(BW RAM) START(0x20088000) END(0x2009ffff) WIDTH(8) }
       mem_L2B2toB4_bw         { TYPE(BW RAM) START(0x20088000) END(0x200a6fff) WIDTH(8) }

    Is this correct?

  • Hi GEFO,

    Yes it is good to modify all the memory blocks which are affected by L2 memory adjustments in ARM core.


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