I am using the Demo uC Project for SHARC ADSP-21569 on the ADZS-21569 EZ-Kit Evaluation Board and currently I have three questions:
- Is there any possibility to increase the memory that can be used for sigma studio schematics exports? The framework defines it with ADI_SS_SHARC_FW_MEMORY to (6272U) in
adi_ss_fw_config_2156x.h. Large and complex schematics will not work anymore if they exceed memory allocations.
- How do I optimize own blocks desinged with the algorithm designer such that the code block is reused with multiple instances? Multiple instances of a parametric EQ for instance adds only once in adi_ss_code_IC_1, only adi_ss_param_IC_1 needs more space.
- If I have an additional audio codec with master clocks, do I need to use the ASRCs to connect and synchronize to these clocks, even if the sample rate is the same? Or is it possible to synchronize the DAI ports to the external clock without ASRCs as it works with the ADAU1466? Maybe I had some configuration wrong: I heard audio but with quantization errors arise time and time again.