Maximum MIPS SC589

Question

Hello, 
 What is the maximum allowable MIPS for the SHARC core in the SC589 in order to opperate properly? I cannot seem to find this info anywhere.

Sakthi^vel · Accepted Answer

Hi Robrechtb, 
 The maximum allowable MIPS may vary based on I/O channel configuration and schematic block size. The default SigmaStudio for SHARC demo example will take around 18 to 20 MIPS for the target framework and the available MIPS for the schematic is up to 420 to 430 MIPS in each SHARC core(core clock is 450 MHz). 
 Thanks.)

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Maximum MIPS SC589