Sigma Studio HW Framework Bit Clock Parity
I have a SS project where I have assigned 2 SPORTs to output to 4 channels in external DACs.
If I set bit clock parity ro Rising instead of Falling I get a factor of 2 higher DAC output signal level.
Why is this? Does this indicate what is Right or Wrong for my DACs?
My DACs are ESS ES9023 and I am not sure how to handle bit clock parity from the data sheet specs.
I have a ADSP-SC589 EZ-Board connected to the outside world via a ADZS-BRKOUT-EX3 board.