Hi again,
I write another post where i ask support for ASRC TDM8 mode with sigma studio framwork (here https://ez.analog.com/dsp/software-and-development-tools/sigmastudio-for-sharc/f/q-a/536980/sharc-21569-asrc-configuration-sigma-studio)
So i reduce my ambitions and try to simply the setup and align it to example.
I configure all the chain to have 2 channels, my signal is 48KHz signal where transition for data and lr clock are on falling edge and sampling on the raising edge with 1 bit clock delay.
This is my setup:
- CCES 2.9.1
- Sigma Studio & Plugin for SHARC 4.5
- Custom Board / Eval 21569-EZKIT
i have async LR clock on DAI0_PB04, the Bit Clock on DAI0_PB03 and TDM data on DAI0_PB01.
I use SRC 0 as sample rate converter and configure it in adi_ss_fw_asrc.c as follow :
pSsFwAsrc->oConfigAsrc.eAsrcBlkNum = ADI_SS_HAL_ASRC_BLK_0;
pSsFwAsrc->oConfigAsrc.eAsrcDeviceNum =ADI_SS_HAL_ASRC_0;
pSsFwAsrc->oConfigAsrc.eAsrcInputFormat = ADI_SS_HAL_ASRC_INPUT_I2S;
pSsFwAsrc->oConfigAsrc.eAsrcOutputFormat = ADI_SS_HAL_ASRC_OUTPUT_I2S;
pSsFwAsrc->oConfigAsrc.eAsrcWordLen = ADI_SS_HAL_ASRC_WORD_LENGTH_24;
I use PGCA as internal clock configured as I2S in adi_ss_fw_audioIO
My SRU configuration is the fallow :
ASRC
Bit Clock input (async from external device 24Mhz)
DAI0_PB03_O -> SRC0_CLK_IP_I
Bit Clock output (synk to internal PCG)
PCG0_CLKA_O -> SRC0_CLK_OP_I
Fs Clock input (async from external device 48KHz / 96 Khz)
DAI0_PB04_O -> SRC0_FS_IP_I
Fs Clock output (synk to internal PCG)
PCG0_FSA_O -> SRC0_FS_OP_I
DAI0_PB01_O -> SRC0_DAT_IP_I
SRC0_DAT_OP_O -> DAI0_PB05
//here i try also to route SRC0_DAT_OP_O directly to the SPORT D0 but looking at eval example i think that this is the way to select the "DAI Pin For Data" pin in sigma studio "Framework Config"
Can you exaplain please ?
SPORT
I'm using SPORT0A to handle the signal
PCG0_CLKA_O -> SPT0A_CLK_I
PCG0_FSA_O -> SPT0A_FS_I
DAI0_PB02_O -> SPT0A_D0_I
Pin Configuration :
DAI0_LOW -> DAI0_PBEN01_I
DAI0_HIGH -> DAI0_PBEN05_I
DAI0_LOW -> DAI0_PBEN03_I
DAI0_LOW -> DAI0_PBEN04_I
The Async LR clock and data did transition on falling edge and sampling on rising edge with 1 blk delay.
The only supported configuration for ASRC input/output format are i2s, lef/right justified, tdm.
How i must handle clock polarities ?
On Sigma Studio "Framwork Config" i setup SPORT0 A as follow (keeping the same edges of the origininal input signal) :
LRCLK Pol : Rising Edge
Bit CLK Pol : Rising Edge
Dai Pin for Data : DAI0 PIN5
Channel num : 8
Serial W Len : 32
I'm not able to see any data on the signal flow, but of course i have data on async I2S data pin.
What i'm wrong? Thank you in advance.
