SHARC 21569 ASRC i2s Configuration Sigma Studio

Hi again,
I write another post where i ask support for ASRC TDM8 mode with sigma studio framwork (here https://ez.analog.com/dsp/software-and-development-tools/sigmastudio-for-sharc/f/q-a/536980/sharc-21569-asrc-configuration-sigma-studio)

So i reduce my ambitions and try to simply the setup and align it to example.
I configure all the chain to have 2 channels, my signal is 48KHz signal where transition for data and lr clock are on falling edge and sampling on the raising edge with 1 bit clock delay.

This is my setup: 
- CCES 2.9.1
- Sigma Studio & Plugin for SHARC 4.5
- Custom Board / Eval 21569-EZKIT


i have async LR clock on DAI0_PB04, the Bit Clock on DAI0_PB03 and TDM data on DAI0_PB01.


I use  SRC 0 as sample rate converter and configure it in adi_ss_fw_asrc.c as follow : 

        pSsFwAsrc->oConfigAsrc.eAsrcBlkNum       = ADI_SS_HAL_ASRC_BLK_0;

        pSsFwAsrc->oConfigAsrc.eAsrcDeviceNum    =ADI_SS_HAL_ASRC_0;

        pSsFwAsrc->oConfigAsrc.eAsrcInputFormat  = ADI_SS_HAL_ASRC_INPUT_I2S;

        pSsFwAsrc->oConfigAsrc.eAsrcOutputFormat = ADI_SS_HAL_ASRC_OUTPUT_I2S;

        pSsFwAsrc->oConfigAsrc.eAsrcWordLen      = ADI_SS_HAL_ASRC_WORD_LENGTH_24;


I use PGCA as internal clock configured as I2S in adi_ss_fw_audioIO 

My SRU configuration is the fallow : 

ASRC

Bit Clock input (async from external device 24Mhz)
DAI0_PB03_O   -> SRC0_CLK_IP_I

Bit Clock output (synk to internal PCG)
PCG0_CLKA_O -> SRC0_CLK_OP_I

Fs Clock input (async from external device 48KHz / 96 Khz)
DAI0_PB04_O   -> SRC0_FS_IP_I

Fs Clock output (synk to internal PCG)
PCG0_FSA_O -> SRC0_FS_OP_I

DAI0_PB01_O -> SRC0_DAT_IP_I

SRC0_DAT_OP_O -> DAI0_PB05

//here i try also to route SRC0_DAT_OP_O directly to the SPORT D0 but looking at eval example i think that this is the way to select the "DAI Pin For Data" pin in sigma studio "Framework Config"
Can you exaplain please ?

SPORT

I'm using SPORT0A to handle the signal

PCG0_CLKA_O -> SPT0A_CLK_I
PCG0_FSA_O -> SPT0A_FS_I
DAI0_PB02_O -> SPT0A_D0_I


Pin Configuration :

DAI0_LOW -> DAI0_PBEN01_I
DAI0_HIGH -> DAI0_PBEN05_I 
DAI0_LOW -> DAI0_PBEN03_I
DAI0_LOW -> DAI0_PBEN04_I


The Async LR clock and data did transition on falling edge and sampling on rising edge with 1 blk delay.

The only supported configuration for ASRC input/output format are i2s, lef/right justified, tdm.
How i must handle clock polarities ?

On Sigma Studio "Framwork Config" i setup SPORT0 A as follow (keeping the same edges of the origininal input signal) :

LRCLK Pol : Rising Edge
Bit CLK Pol : Rising Edge
Dai Pin for Data : DAI0 PIN5
Channel num : 8
Serial W Len : 32

I'm not able to see any data on the signal flow, but of course i have data on async I2S data pin.

What i'm wrong? Thank you in advance.

  • Hi shooks,

    Could you please refer following link for 96K SigmaStudio for SHARC framework support and let me know any progress?


    https://ez.analog.com/dsp/software-and-development-tools/sigmastudio-for-sharc/f/q-a/120756/building-a-96k-192k-version-of-ss_app_core-for-adsp-sc58x-ez-board

    Also you need to do following modifications to ASRC output data pins,

    File: adi_ss_fw_sport.c

    Function: RouteSPORTSignalData()

    Line: 396

    #elif defined(__ADSP2156x__)
    if((ePinGroup==ADI_SS_FW_DAI_PIN_GROUP_0) && (eDAIDatPinVal == ADI_SS_DAI_PIN05))
    #endif
    {
    *pDAIPBEN |= ((uint32_t)DAI_HIGH << nDAIPBENShift);
    }

     

    Thanks.

  • Hi Sakthi^vel,
    Thank you for your response.

    I don't have any problem for 96KHz, just configure my adc/dac for 96KHz and sigma studio provide parameter for PCG initialization.

    About my question i don't understand your suggestion and maybe there is something that i miss.
    The RouteSPORTSignalData() function ( in file adi_ss_fw_sport.c ) seem to route my dai pin again because i already did my SRU connection on system.svc (that generate sru_config.c) that is called while initialize adi components (adi_initialize) and i don't understand the routing that we are doing on RouteSPORTSignalData.

    Can you please provide, if it exist, the name of a Simple Example (hopefully one of example provided with CEES) that can help me understand what happen in the code behind RouteSPORTSignalClkFS and  RouteSPORTSignalData?
    I already study ASRC_I2S_MODE and Audio_Passthrough_I2S_21569 but evidently something is not clear for me.

    Thank you in advance.


     

  • Hi shooks,

    Now I got what could be the reason for your issue, can you please make following change and let me know the status,

    File: adi_ss_fw_audioIO.c

    Function: PADS_Init()

    Change code,

    #elif defined (__ADSP2156x__)
    *pREG_PADS0_DAI0_IE=0x1ffffeU;
    *pREG_PADS0_DAI1_IE=0x1ffffeU; 

    to 

    #elif defined (__ADSP2156x__)
    *pREG_PADS0_DAI0_IE=0x1fffffU;
    *pREG_PADS0_DAI1_IE=0x1fffffU; 

    The DAI0 PIN1 buffer not enabled for input, so the data not available in DAI0 Pin 1.

    Regarding other queries, 

    The RouteSPORTSignalData() is used to route the data pin to SPORT input based on SigmaStudio Host configuration.

    The RouteSPORTSignalClkFS() is used to route the CLK and FS to SPORT based on SigmaStudio Host configuration for I2S or TDM format.

    Thanks.