SHARC 21569 ASRC configuration Sigma Studio

Hi all,
I'm trying to setup a SHARC 21569 with an async TDM input using sigma studio framework.

This is my setup: 
- CCES 2.9.1
- Sigma Studio & Plugin for SHARC 4.5
- Custom Board / Eval 21569-EZKIT


i have async LR clock on DAI0_PB04, the Bit Clock on DAI0_PB03 and TDM data on DAI0_PB01.

I use a chain of SRC 0/3 as sample rate converter and configure it in adi_ss_fw_asrc.c as follow : 

        pSsFwAsrc->oConfigAsrc.eAsrcBlkNum       = ADI_SS_HAL_ASRC_BLK_0;

        pSsFwAsrc->oConfigAsrc.eAsrcDeviceNum    = idx; // in a loop from 0 to 3

        pSsFwAsrc->oConfigAsrc.eAsrcInputFormat  = ADI_SS_HAL_ASRC_INPUT_TDM;

        pSsFwAsrc->oConfigAsrc.eAsrcOutputFormat = ADI_SS_HAL_ASRC_OUTPUT_TDM;

        pSsFwAsrc->oConfigAsrc.eAsrcWordLen      = ADI_SS_HAL_ASRC_WORD_LENGTH_24;


I use PGCB as internal clock configured as TDM8 in adi_ss_fw_audioIO 

        pPCGConfig->nSamplingFrequency  = pSSFWAudioIO->oSignalInfo.oPinGroupIn.aoPinInfo[0].nSamplingRate;

       
/*pPCGConfig->nNumChannels        = NUM_CHANNELS_I2S;
        pPCGConfig->nEnFsPhase          = ADI_SS_FW_PCG_ENABLE_FS_PHASE;*/

        pPCGConfig->nNumChannels        = NUM_CHANNELS_TDM8;

        pPCGConfig->nEnFsPhase          = ADI_SS_FW_PCG_DISABLE_FS_PHASE;

        pPCGConfig->nInitPwSync         = ADI_SS_FW_PCG_PW_SYNC_INIT;

        pPCGConfig->nEnExtInputClk      = ADI_SS_FW_PCG_ENABLE_EXT_CLK;

        pPCGConfig->nExtClk             = ADI_SS_FW_PCG_EXT_CLKIN_FREQ_24576000HZ;

        pPCGConfig->nPulseWidth2        = ADI_SS_FW_PCG_PW2_FSC;


i have master clock on DAI1_PB03 on PCG C and use DAI0_CSR_PB03 to share the clock between PCG C and PGC A/B
(clock are verified)

My SRU configuration is the fallow : 

ASRC

Bit Clock input (async from external device 24Mhz)
DAI0_PB03_O   -> SRC0_CLK_IP_I
DAI0_PB03_O   -> SRC1_CLK_IP_I
DAI0_PB03_O   -> SRC2_CLK_IP_I
DAI0_PB03_O   -> SRC3_CLK_IP_I

Bit Clock output (synk to internal PCG)
PCG0_CLKA_O -> SRC0_CLK_OP_I
PCG0_CLKA_O -> SRC1_CLK_OP_I
PCG0_CLKA_O -> SRC2_CLK_OP_I

PCG0_CLKA_O -> SRC3_CLK_OP_I

Fs Clock input (async from external device 48KHz / 96 Khz)
DAI0_PB04_O   -> SRC0_FS_IP_I
DAI0_PB04_O   -> SRC1_FS_IP_I
DAI0_PB04_O   -> SRC2_FS_IP_I
DAI0_PB04_O   -> SRC3_FS_IP_I

Fs Clock output (synk to internal PCG)
PCG0_FSA_O -> SRC0_FS_OP_I
PCG0_FSA_O -> SRC1_FS_OP_I
PCG0_FSA_O -> SRC2_FS_OP_I
PCG0_FSA_O -> SRC3_FS_OP_I


DAI0_PB01_O -> SRC0_DAT_IP_I

SRC0_TDM_OP_O -> SRC1_DAT_IP_I
SRC1_TDM_OP_O -> SRC2_DAT_IP_I
SRC2_TDM_OP_O -> SRC3_DAT_IP_I
SRC3_DAT_OP_O -> DAI0_PB02

//here i try also to route SRC3_DAT_OP_O directly to the SPORT D0 but looking at eval example i think that this is the way to select the "DAI Pin For Data" pin in sigma studio "Framework Config"
Can you exaplain please ?

SPORT

I'm using SPORT0A to handle the signal

PCG0_CLKA_O -> SPT0A_CLK_I
PCG0_FSA_O -> SPT0A_FS_I
DAI0_PB02_O -> SPT0A_D0_I


Pin Configuration :

DAI0_LOW -> DAI0_PBEN01_I
DAI0_HIGH -> DAI0_PBEN02_I 
DAI0_LOW -> DAI0_PBEN03_I
DAI0_LOW -> DAI0_PBEN04_I


The Async signal arrive on the async TDM data with LR Clock Rising and Bit Clock Rising with 1 BT Clock Delay.

The only supported configuration for ASRC input/output format are i2s, lef/right justified, tdm.
How i must handle clock polarities ?

On Sigma Studio "Framwork Config" i setup SPORT0 A as follow (keeping the same edges of the origininal input signal) :

LRCLK Pol : Rising Edge
Bit CLK Pol : Rising Edge
Dai Pin for Data : DAI0 PIN2
Channel num : 8
Serial W Len : 32

I'm not able to see any data on the signal flow, but of course i have data on async TDM data pin.

What i'm wrong? Thank you in advance.

 








Add a schema to explain better
[edited by: shooks at 5:39 PM (GMT -4) on 25 Oct 2020]