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SigmaStudio 4 SharC ADSP-21569 sample rate

Dear all,

I would like to change the sample rate from 48KHZ to 96KHz in the example Volume_Mute_Block_2156x.dspproj.

The purpose is to run the example in "Advanced Design Mode and Tuning" or "Deployment Mode" ...

To do so, I suppose to I have to make changes in the example code provided for the target "C:\...\Target\Examples\DemoUc\ADSP-2156x\ADSP-21569\SS_uC_App_Core1\Release\SS_uC_App_Core1.dxe" by using "CCES".

I have tried to change directly the sample Rate through SigmaStudio and recompile the SS_uC_App_Core1 example with "CCES" then flash it and run it from the flash in "Deployment Mode"  but unfortunately when after all those steps the example does not work.

I would like to understand, if I have to modify a specific structure in the Target Example considering that the field " bHostConfigEn" in the structure "struct ADI_SS_FW_HOST_CONFIG" is enabled!

Please, could you advise the right steps to change the Sample rate...
Thank you in advance,

My environment's tools:

 - SigmaStudioForSHARC-SH-Rel4.5.0

- CCES 2.9.2

- DSP: ADSP-21569

- ADZS-21569-EZKIT

  • Hi Yuka,

    Since ADSP-215xx/ADSP-SC5xx have common target framework files in example applications, You can refer the following link which is having detailed information's regarding  sample rate change in target example other than SigmaStudio schematic sample rate change.

    Target application sample rate change:

    Regenerating SigmaStudio schematic source files for DemoUc example:

    You can run modified DemoUc application by regenerating the “Volume_Mute_Block “ SigmaStudio schematic source files with modified and built DXE as SHARC core “Application DXE”.

    Please refer sections,

    7.2.2 Custom schematic for ADSP-2156x and  “A. Utility for formatting Exported data from SigmaStudio” in “AE_42_SS4G_QuickStartGuide.pdf” for generating schematic source files.


  • Dear Sakthi^vel,

    Thanks for your reply,

    Unfortunately, I followed and applied the changes for my SS_App_Core1 application as you suggested above but without success. I am always not able to output sound when changing the sample rate from 48KHZ to 96KHZ.
    I checked out the following points:
    1 - Inside AudioIoPcgInit function, I set the Channels numbers
    pPCGConfig->nNumChannels       = NUM_CHANNELS_TDM4;
    2 - The DAC and ADC have been configured to support the TDM4.

    3 - The sigma Studio framework configuration is as follow:

    SS Framework configuration for 96Khz TDM4

    4 - The sigma Studio Main tab configuration is as follow:

    Main configuration tab

    The example schematic below is quite simple to illustrate:
    My purpose is to set as input 1 analog signal (L or R) then split the signal in 2 output as 2 channels ch0 and ch1.
    ch0 for the tweeter and ch1 for the woofer.

    Could you advise if I missed something in my configuration to get the sample rate at 96Khz?

  • Hi Yuka,
    Please try the following steps,

     1. Change the Input / output  channels to 4, since the ADC/DAC operating mode set to TDM4. 

    2. Change the following preprocessor macro to set block size as in schematic,

    C:\Analog Devices\SoftwareModules\SigmaStudioForSHARC-SH-Rel4.5.0\Target\Examples\Framework\Include\ "adi_ss_fw_common.h"




    3. Regenerate "adi_ss_fw_config_2156x.h" file using " IC 1 - ADSP-SC5xx Control  -- Framework Config -- Generate Config File" option and replace the file in following folder 

    C:\Analog Devices\SoftwareModules\SigmaStudioForSHARC-SH-Rel4.5.0\Target\Examples\Framework\Include\ " adi_ss_fw_config_2156x.h"

    4. Rebuild the ADSP-21569 example demo application in Release/Debug build configuration and select the same DXE in SigmaStudio schematic for SHARC0. 


  • Dear Sakthi^vel,

    Thanks a lot for your answer,

    Unfortunately, I already made these changes.

    Currently, it's the configuration that I am using and I still get no output sound with the sample rate at 96Khz.

    Do you mind if I send you the source code to test on your side? If you agree let me know where I could put the source code.

    Thank you in advance,


  • Hi Yuka,
    May be some points missed in that Q&A discussion which I directed. Please refer and try the following steps once, it works for me.

    The Required Target Framework Modifications for Block Size Change, Sample Rate Change and TDM4 Configurations:

    1. Change the required FW Process Block Size

    File: adi_ss_fw_common.h

    #define ADI_SS_FW_MAX_PROCESS_BLOCKSIZE  (1024U)  /*!< Maximum number of samples that can be processed per call (BLOCK_SIZE) *

    1. Change the required system sample rate for ADC and DAC in

    File: adi_ss_app_system.c

    Function: adi_ss_system_initialize()

    pSysConfig->eAdcSamplingRate = ADI_SS_SYS_SR_96000;

    pSysConfig->eDacSamplingRate = ADI_SS_SYS_SR_96000;

     For adding sample rate “ADI_SS_SYS_SR_96000” need to update following file,

    File: adi_ss_sys.h

    #define E_ADI_SS_SYS_SR_48000         (0U)

    #define E_ADI_SS_SYS_SR_96000         (1U)

    typedef enum ADI_SS_SYS_SAMPLERATE


        ADI_SS_SYS_SR_48000         = E_ADI_SS_SYS_SR_48000,

        ADI_SS_SYS_SR_96000         = E_ADI_SS_SYS_SR_96000



    1. Change the required sample rates for ADC in,

    File: adi_ss_sys_adc.c

    Function: ADC_Init()



        case ADI_SS_SYS_ADC_SR_48000:

    pSysAdc->oConfigADCHAL.eSampleRate =    ADI_SS_HAL_ADAU1979_SAMPLE_RATE_48000HZ;


        case ADI_SS_SYS_ADC_SR_96000:

    pSysAdc->oConfigADCHAL.eSampleRate =    ADI_SS_HAL_ADAU1979_SAMPLE_RATE_96000HZ;



            return ADI_SS_SYS_ADC_FAILED;


     For adding sample rate “ADI_SS_SYS_ADC_SR_96000” need to update following file,

    File: adi_ss_sys_adc.h

    #define E_ADI_SS_SYS_ADC_SR_48000   (0U)

    #define E_ADI_SS_SYS_ADC_SR_96000   (1U)

    typedef enum ADI_SS_SYS_ADC_SAMPLERATE


        ADI_SS_SYS_ADC_SR_48000  = E_ADI_SS_SYS_ADC_SR_48000, /*!< Enum for sampling rate of 48000. */

    ADI_SS_SYS_ADC_SR_96000  = E_ADI_SS_SYS_ADC_SR_96000 /*!< Enum for sampling rate of 96000. */



    1. Change the required sample rates for DAC in,

    File: adi_ss_sys_dac.c

    Function: DAC_Init ()



        case ADI_SS_SYS_DAC_SR_48000:

    pSysDac->oConfigDACHAL.eSampleRate = ADI_SS_HAL_ADAU1962A_SAMPLE_RATE_48000HZ;


        case ADI_SS_SYS_DAC_SR_96000:

    pSysDac->oConfigDACHAL.eSampleRate = ADI_SS_HAL_ADAU1962A_SAMPLE_RATE_96000HZ;



            return ADI_SS_SYS_DAC_FAILED;


     For adding sample rate “ADI_SS_SYS_DAC_SR_96000” need to update following file,

    File: adi_ss_sys_dac.h

    #define E_ADI_SS_SYS_DAC_SR_48000   (0U)

    #define E_ADI_SS_SYS_DAC_SR_96000   (1U)

    typedef enum ADI_SS_SYS_DAC_SAMPLERATE


    ADI_SS_SYS_DAC_SR_48000  = E_ADI_SS_SYS_DAC_SR_48000, /*!< Enum for sampling rate of 48000. */

    ADI_SS_SYS_DAC_SR_96000  = E_ADI_SS_SYS_DAC_SR_96000 /*!< Enum for sampling rate of 96000. */


    1. Change the ADC and DAC System sample rate configuration in

    File: adi_ss_sys.c

    Function: adi_ss_sys_Init ()

    /* ADC configuration */



            case ADI_SS_SYS_SR_48000:

                oAdcConfig.eAdcSamplingRate = ADI_SS_SYS_ADC_SR_48000;


    case ADI_SS_SYS_SR_96000:

                 oAdcConfig.eAdcSamplingRate = ADI_SS_SYS_ADC_SR_96000;



                return ADI_SS_SYS_FAILURE;



    /* DAC configuration */



            case ADI_SS_SYS_SR_48000:

                oDacConfig.eDacSamplingRate = ADI_SS_SYS_DAC_SR_48000;


            case ADI_SS_SYS_SR_96000:

                oDacConfig.eDacSamplingRate = ADI_SS_SYS_DAC_SR_96000;



                return ADI_SS_SYS_FAILURE;



    1. Change the PCG sample rate configuration in,

    File: adi_ss_fw_audioIO.c

    Function: AudioIOInputPin_Init ()

            /* Configure PCG C/ PCG B (ADSP-2157x) */

            /* PCG C/PCG B (in case of ADSP-2157x) is always configured to provide clock for TDM 8 configuration */

    pPCGConfig->nSamplingFrequency  = pSSFWAudioIO->oSignalInfo.oPinGroupIn.aoPinInfo[0].nSamplingRate;

            pPCGConfig->nNumChannels        = NUM_CHANNELS_TDM4;


    1. Change the DAC sample rate configurations

    File: adi_ss_hal.c

    Static configuration as for TDM4,

    static struct ConfigTable ConfigArrayDAC[ADI_SS_HAL_ADAU1962A_NUM_REG] = {

    {     ADI_SS_HAL_ADAU1962_PDN_CTRL_1,                0xa4 },

    {     ADI_SS_HAL_ADAU1962_PDN_CTRL_2,        0x00 },  //Power down DAC

    {     ADI_SS_HAL_ADAU1962_PDN_CTRL_3,        0x00 }, //Power down DAC

    {     ADI_SS_HAL_ADAU1962_DAC_CTRL0,                  0x13 }, //TDM4 96KHz


    1. Change the ADC sample rate configurations

    File: adi_ss_hal.c

    Static configuration as for TDM4,

    static struct ConfigTable ConfigADC[ADI_SS_HAL_ADAU1979_NUM_REG] = {

      {ADI_SS_HAL_ADAU1979_REG_BLOCK_POWER_SAI   ,           0xb0},//power down ADC LDO enable

     {ADI_SS_HAL_ADAU1979_REG_SAI_CTRL0    ,           0x53},//TDM4 96KHz

     {ADI_SS_HAL_ADAU1979_REG_SAI_CTRL1                            ,           0x08},//LRCLK pulse mode //original value =08


    The Required SigmaStudio schematic Modifications for Block Size Change, Sample Rate Change and TDM4 Configurations:

    1. Modify the Block schematic FS to 96KHz

              In SigmaStudio create new schematic and change the FS to 96KHz using “Set System Sample Rate” tool bar option.


    1. Modify the Block schematic for 4ch input and 4 Ch output, Also Modify the Block Size

            In SigmaStudio schematic main window change Input Channels and Output Channels to 4, also modify the Block size to 1024

    3. Modify the Framework configuration for TDM4 with 1 Source and 1 Sink

    In SigmaStudio schematic Framework Config window change the framework configuration for ADC Source as,


    In SigmaStudio schematic Framework Config window change the framework configuration for DAC Sink as,

     4. Create Simple block schematic,



    The General Steps Required After Modifications for Block Size Change, Sample Rate Change and TDM4 Configurations:

    1. Generate Framework Config File from SigmaStudio,

                  In SigmaStudio schematic Framework Config window use “Generate Config File” to generate framework configuration file as “adi_ss_fw_config_2156x.h” and save it to “C:\Analog Devices\SoftwareModules\SigmaStudioForSHARC-SH-Rel4.5.0\Target\Examples\Framework\Include” folder.

    1. Rebuild the Target Framework Application
    2. In SigmaStudio schematic Select the Rebuilt DXE
    3. Run Target and Do Link Compile Download Schematic
    4. Connect Audio Input to ADC and Check Output of DAC


  • Dear Sakthi^vel,

    Thanks a lot for your clear description,

    Now everything is working smoothly in 96Khz.

    My mistake was to do not change the register value of the ADC and DAC in the adi_ss_hal.c.

    Just in case, could you let me know where I could find the value If I want to switch to 192Khz sample rate please ?

    We can close the ticket.

    Thanks again.

  • Hi Yuka,

    The ADC(ADAU1979) and DAC (ADAU1962A) register settings can be referred from respective data sheets. Please refer following path,

    ADC(ADAU1979) ADAU1979 (Rev. 0) (

    DAC (ADAU1962A) - ADAU1962A (Rev. A) (


  • Hi Sakthi^vel:

    In SigmaStudio schematic,

    Why am I changing the Block Size to 1024, and what does the Block Size do?

  • Hi,

    The 1024 block size is requirement from Yuka, you can use default block size of 64 itself.