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Building a 96k / 192k version of SS_App_Core for ADSP-SC58x EZ board

Dear support,

The Demo version of SS_App_Core for ADSP-SC58x EZ board supports only 48k sampling rate.

Is it possible to modify the code to support 96k and 192k as well? If YES, how can it be done?

Or is another example available where the support already exist?


  • Sakthi,

    As you may have noticed, I have put this issue aside for a while, I will try to solve the 192k issue later.

    I will now try to solve the functional integration of my application to a standalone solution first.

    This thread can be closed. Thanks for your support.

  • Dear Aakthi^vel,

    I was finally able to get 96k working in TDM8 mode.

    However, since I want to go to 192kHz, I need to change to TDM4.

    I changed TDM in files adi_ss_fw_audioIO.c and adi_ss_hal.c, and also in the SS project firmware, SPORT4A and SPORT5A to TDM4. Keeping 96k for the moment, but no success with TDM4.

    Edit: Changing the number of channels to 4 for SPORT4 and SPORT5 mode TDM4 and 96k work. However, 192k is still not running. So the question remains: I need some suggestions on tuning the SS project FW settings for 192k.

  • A question about channel support and TDM:

    I need 1 analog stereo in, 1 spdif stereo in, and 2 analog stereo out.

    Does TDM4 mean 4 total channels, counting both inputs AND outputs?

    I do not need both analog and spdif inputs simultaneously.

    Will I be able to cover my channel needs using 192k TDM4?

    How can I disable the channels I don't need to get sufficient resources?

  • I was able to generate and use a config file from SS Firmware Setup for the following:

    SPORT4A TDM4 2ch analog in

    SPORT0A 2ch spdif in

    SPORT5A TDM4 4ch analog out

    The SS_uC_App project is running fine with this at 96k with Exports from the SS project. However, I get no signal out when using 192k in the SS project and the SS_uC_App project.

    It seems to be running in Debug 192k, I can see working Version and MIPS for both IC_1 and IC_2 in the SS project FW window. The MIPS value goes down to half when I use "bypass schematic", and there are no messages indicating failures in the console window. But I cannot see any analog output.

    I would appreciate some suggestions on how to troubleshoot why I do not get any signal out.

  • Hi BN,
    I hope that you have done the 192k modifications as the early replies in the same thread which I given for ADC and DAC configuration and modifications for 96k.

    Please try running ADC and DAC playback example with SAMPLE_RATE macro set to 192K, If you are not facing any issue with audio I/O, then your missing some configuration for ADC/DAC in SigmaStudio for SHARC framework.

    Example application: CCES - Help - Browse examples - Select Processor ADSP-SC589 - Select example  ADC DAC Playback SC589 SHARC

    If any settings wrong with ADC or DAC there wont be any input/output signals. Also please check the SCLK and FSCLK signals to ADC and DAC using CRO or any other device.

    Does TDM4 mean 4 total channels, counting both inputs AND outputs?

    [Ans] ADC - TDM4 -  max 4 channels

             SPDIF - I2S -  max 2 channels

    Will I be able to cover my channel needs using 192k TDM4?

    [Ans] yes its possible.

    How can I disable the channels I don't need to get sufficient resources?

    Uncheck input signals which are not required.

    do not connect output signal which are not required.  


  • Thanks for the advice.

    Yes, Playback is working at 192kHz.
    I made a simple project in SigmaStudio, which works at SS sample rate=96k and a 96k SS_App_Core.DXE’s, both referenced in the SigmaStudio Hardware settings and loaded from CCES debugger.
    I use the same SigmaStudio settings as the default example project, except that TDM8 is changed to TDM4, and the number of outputs are reduced to the following:
    Input sources = 2 (Analog and SPDIF)
    Output sinks=1 (Analog)
    Input channels = 4 (2 channels SPDIF, 2 channels Analog in)
    Output channels = 4 (4 channels Analog out)
    I have generated a config file from SS and replaced the default one in the SS_App project. 
    This runs fine at 96k.
    However, if I change to 192k (both in SS project and SS_App_Core) I get no output.
    Something runs, because I can get a MIPS value in the SS Hardware settings which changes to a lower value when I do schematic bypass.
    According to the instructions you have given me, TDM4 and 192k should be supported, and I have not seen any other limitations.
    If there are any other settings I can try in the SS project, please suggest.
    You need to clarify your last suggestion about SCLK, FSCLK and CRO.
    Is CRO simply an oscilloscope?
    Of course I have an oscilloscope, but I need some suggestions on how to find the test points.
    Should I use the BRKOUT card?
    Which pins should I look for?
  • I tried the BRKOUT board and found some signals.

    I now realise that the SPORT pin assignments shown on the schematics are not necessarily true, only the DAIn_PINn are fixed properties. The SPORT functional pin assignments such as CLK, D0, etc. are set by the SRU config. Is this a correct conclusion?

    I have seen data on the DAI pins involved in the audio input and output at 96k, as well as on the analog output.

    When testing the 192k configuration, there were data on the same pins there also, but no analog.

    I have problem locating the pins for SCLK and FSCLK signals. Are they PGC0_CLKC_O and PGC0_FSC_O as seen in the SRU? If they are, they exist and for 192k config they are 24.575MHz and 192kHz respectively.However, no analog output.

    Update 2020-07-04:

    I measured the signals at the 74CBTLV3244 bus switch (according to the schematic), both at 96k and 192k.

    1A1 96k: 12MHz clock, 192k: 24MHz clock

    1A2 96k: 96k sync, 192k: 192k sync

    1A3 96k: data present, 192k: data present

    1A4 96k: quiet, 192k: quiet

    2A1 96k:12Mhz clock, 192k: 24MHz clock

    2A2 96k:96k sync, 192k:192k sync

    2A3: 96k: data, 192k: data

    2A4: 96k: quiet, 192k: quiet

    So the main signals are getting thru, but no analog out for 192k. Of course, there are more pins than these, but they are not as easy to find and measure.


  • I am now trying to study the signal routing of the Playback Demo. In the "ascii-graphic schematic" in the project Readme I can see that the main 25.47MHz clock is connected to DAI03, but there are no connections to DAI03 in the SRU. If I measure with oscilloscope, it is there.

    Could you please comment on this?

  • Hi BN,

    The master clock 24.576 Mhz is connected to ADAU1962A_CLKIN and available in DAI1_PIN03 also.

    You can refer ADSP-SC589 Example demo application project "SS_App_Core0" - system.svc - Signal Routing Unit - Routing details for how the master clock used in application FW.

    DAI1_PBEN03_I  - DAI1_LOW (To configure DAI1_PIN03 as Input pin)

    DAI1_CRS_PB03_O - PCG0_EXTCLKA_I  (Mater clock connected as external input to PCG A for generating I2S CLK and FS. The DAI PIN 3 and PIN 4 have cross connection option to get Signal to other DAI group pins and PCGs)

    DAI1_PB03_O - PCG0_EXTCLKC_I (Mater clock connected as external input to PCG C for generating TDM CLK and FS)

    There after the SCLK and FSCLK connected to other peripherals from respective PCG's.