Building a 96k / 192k version of SS_App_Core for ADSP-SC58x EZ board

I have imported the Demo SS_App_Core again, being very careful regarding the project path settings. Now the project builds without errors, but as soon as I open the source files adi_ss_app_sh0.c, adi_ss_app_sh1.c, adi_ss_app_system.c in the CCES editor window I get red "unresolved symbols" errors. 

I have made the suggested modifications in files:

adi_ss_sys.c, adi_ss_sys.h

adi_ss_app_system.c

adi_ss_sys_adc.c, adi_ss_sys_adc.h

adi_ss_sys_dac.c, adi_ss_sys_dac.h

and also in 

adi_ss_hal.c

Now please explain the meaning of "check for the significance of this sample rate variable and modify FW accordingly".

The project "ADC_DAC_Playback_SC589_SHARC_Core*" required only change of two lines to work at 192k. This playback project does NOT involve SigmaStudio. Is "modify FW accordingly" related to the SigmaStudio project settings?

In the SigmaStudio project, I set the executables for SHARC0 and SHARC1 to SS_App_Core1/Debug/SS_App_Core1.dxe and SS_App_Core2/Debug/SS_App_Core2.dxe respectively, no other settings are changed. The SigmaStudio project is set as DualCore. In the unmodified 48k version this works fine. If I compile and build the 192k debug version of the dxe in CCES (without errors) it STILL works at 48k in SigmaStudio. If I set the SigmaStudio project to use 192k I get no output.

This is the Firmware settings of my SigmaStudio project:

Is this appropriate for 192k sampling frequency?

There is an older thread https://ez.analog.com/dsp/sigmadsp/f/q-a/67458/how-do-i-change-the-sample-rate-of-my-sigmastudio-system touching this issue in detail. However, it does not cover this hardware. It would be nice to see something similar for the ADSP-SC589 EZ board.

Thanks.

As I said earlier, ADSP-SC589 EZ-kit can support TDM4 for 4 ch with 192K sample rate, Please follow the steps to setup the Clock and channel configuration,

1. Demo application modify the number of channels from TDM8 to TDM4 in file adi_ss_fw_audioIO.c. refer the image.

2. In SigmaStudio framework configuration modify the Source 1 and Sink 1 SPORT settings as 

operation mode TDM4 and number of channels can be 4. The second source meant for I2S input from SPDIF source don't modify the settings. 

3. Change the schematic sample rate to 192K (Demo application uses this sample rate as I/O sample rate for configuring the clock )

4. rebuild the demo application, use the generated DXE's in SigmaStudio schematic and run the target with SigmaStudio.

I hope this changes work for 192K sample rate with demo application.

Thanks.

Thanks, I have already tested 1 and 3. without success.

However, the SigmaStudio framework config I have not done and I hope this will be the last piece in the puzzle.

Sakthi^vel said:

In SigmaStudio framework configuration modify the Source 1 and Sink 1 SPORT settings as 

operation mode TDM4 and number of channels can be 4.

Unfortunately, don't understand the above. Can you show it in a screen shot, like the one I posted?

During this long discussion, I came up with another question. In the QuickStart guide, the initial flashing process includes Core0.exe, Core1.dxe and Core2.dxe. How does this flashing relate to the Cores we now build for 192kHz? Should I flash again with the 192kHz Cores?

Please find the SigmaStudio SPORT settings,

Regarding Flash, you should generate LDR file with latest dxe's and flash again to target.

Please find some more modifications needs to be done on application framework ADC and DAC configuration,

1. DAC TDM4 configuration,

2. ADC TDM4 configuration,

The same way you need to check if we missed any ADC/DAC configurations for 192K.

Thanks.

Thanks for the news. However no luck yet.

I am now starting over.

I have removed and re-installed all software (CCES, SS, add-ins, etc.) just to be sure I have not accidentally damaged anything. I have re-flashed using the prebuilt Cores012 delivered with the installation, as described in the QuickStartGuide. I am testing the simplest possible 48k SS project (Analog input ports directly connected to output ports in the block schematics), and I notice one interesting thing:

When the FW configured as "dual core" everything works as expected, my oscilloscope shows output..

When the FW configured as "single core - Core 1" I get no output.

When the FW configured as "single core - Core 2" I get output sometimes, not consistent.

SPORTs and channels are default, TDM8 (SPORT4A 6 channels and SPORT 5A 8 channels)

This worries me for the 192k test, since the FW config seems not to be limited to only TDM4 and 4 channels, more things matter. What is the safest mode when testing 192k? Is it "dual core"?

What could be the reason for my single core problem when using the default 48k mode?

Can you recommend some reading for me to sort this out? I have been reading the docs delivered, but I have not yet found what I am looking for. The built-in SS help is empty, and links only to a web help, where some of the content is "under construction", a bit dated, and no entries for my ADSP-SC589 hardware.

I have now rebuilt the 192k cores according to your instructions, and flashed.

In my SS DualCore 192k project, I can see MIPS≈20 , so something is running, but I have no output.

If I want to debug the SS_App_Cores with CCES, should I flash the Debug versions instead of the Release?

You can run and debug application in CCES through ICE-1000 or ICE-2000 emulator mode with debug build configuration, also you can put break points in functions which you want to debug. All the variables can be viewed in debug session when stepping into the functions. Please follow the steps 1 to 17 in "AE_42_SS4G_QuickStartGuide.pdf" section "9.1 Steps to be followed to Debug a function in the schematic ".

If you want debug the application in flash, application should be build with debug configration and flashed to the target. The steps can be followed as above but you should select only "load symbols only" (step 14) option for all core dxe's while creating debug session.