Building a 96k / 192k version of SS_App_Core for ADSP-SC58x EZ board

Dear support,

The Demo version of SS_App_Core for ADSP-SC58x EZ board supports only 48k sampling rate.

Is it possible to modify the code to support 96k and 192k as well? If YES, how can it be done?

Or is another example available where the support already exist?

BN

Parents
  • There is no example available with 96K or 192K sample rate. You need to modify the example demo application to 96K or 192K based on your requirement. Please refer the following information's how to modify the  example demo application,

    1. The maximum clock range is 24.567MHz in ADSP-SC5xx EZ board, please refer corresponding EZ board harware schematic. You can find the EZ board harware schematic from "https://www.analog.com" by entering processor name as keyword in search. e.g. ADSP-SC589

    The maximum Channels support are,

    48K - TDM16

    96K - TDM8

    192K - TDM4

    2. Modify the SigmaStudio schematic sampling rate to 96K or 192K. Modify the framwork configuration for the SPORT by considering maximum channel support possible with chosen FW sample rate.

    3. Modify the number of channels support in FW application function AudioIoPcgInit() in file adi_ss_fw_audioIO.c

    4. Modify the sample rate support and configurations of ADC and DAC with respect to sample rate. Go through the function adi_ss_system_initialize() in file adi_ss_app_system.c. The ADC and DAC configuration can be done by referring data sheet. You can find the datasheet from "">https://www.analog.com" by entering ADC or DAC name as keyword in search. e.g. ADAU1979 or ADAU1966A

    5. You can verify the FW modification by running application in CCES debug session with build configuration as Debug.

    6. If all configurations is fine then run application and download SigmaStudio schematic.

    Thanks.

  • A question about channel support and TDM:

    I need 1 analog stereo in, 1 spdif stereo in, and 2 analog stereo out.

    Does TDM4 mean 4 total channels, counting both inputs AND outputs?

    I do not need both analog and spdif inputs simultaneously.

    Will I be able to cover my channel needs using 192k TDM4?

    How can I disable the channels I don't need to get sufficient resources?

  • Hi BN,
    I hope that you have done the 192k modifications as the early replies in the same thread which I given for ADC and DAC configuration and modifications for 96k.

    Please try running ADC and DAC playback example with SAMPLE_RATE macro set to 192K, If you are not facing any issue with audio I/O, then your missing some configuration for ADC/DAC in SigmaStudio for SHARC framework.

    Example application: CCES - Help - Browse examples - Select Processor ADSP-SC589 - Select example  ADC DAC Playback SC589 SHARC

    If any settings wrong with ADC or DAC there wont be any input/output signals. Also please check the SCLK and FSCLK signals to ADC and DAC using CRO or any other device.

    Does TDM4 mean 4 total channels, counting both inputs AND outputs?

    [Ans] ADC - TDM4 -  max 4 channels

             SPDIF - I2S -  max 2 channels

    Will I be able to cover my channel needs using 192k TDM4?

    [Ans] yes its possible.

    How can I disable the channels I don't need to get sufficient resources?

    Uncheck input signals which are not required.

    do not connect output signal which are not required.  

    Thanks.

  • Thanks for the advice.

    Yes, Playback is working at 192kHz.
    I made a simple project in SigmaStudio, which works at SS sample rate=96k and a 96k SS_App_Core.DXE’s, both referenced in the SigmaStudio Hardware settings and loaded from CCES debugger.
    I use the same SigmaStudio settings as the default example project, except that TDM8 is changed to TDM4, and the number of outputs are reduced to the following:
    Input sources = 2 (Analog and SPDIF)
    Output sinks=1 (Analog)
    Input channels = 4 (2 channels SPDIF, 2 channels Analog in)
    Output channels = 4 (4 channels Analog out)
    I have generated a config file from SS and replaced the default one in the SS_App project. 
    This runs fine at 96k.
    However, if I change to 192k (both in SS project and SS_App_Core) I get no output.
    Something runs, because I can get a MIPS value in the SS Hardware settings which changes to a lower value when I do schematic bypass.
    According to the instructions you have given me, TDM4 and 192k should be supported, and I have not seen any other limitations.
    If there are any other settings I can try in the SS project, please suggest.
    You need to clarify your last suggestion about SCLK, FSCLK and CRO.
    Is CRO simply an oscilloscope?
    Of course I have an oscilloscope, but I need some suggestions on how to find the test points.
    Should I use the BRKOUT card?
    Which pins should I look for?
    BN
  • I tried the BRKOUT board and found some signals.

    I now realise that the SPORT pin assignments shown on the schematics are not necessarily true, only the DAIn_PINn are fixed properties. The SPORT functional pin assignments such as CLK, D0, etc. are set by the SRU config. Is this a correct conclusion?

    I have seen data on the DAI pins involved in the audio input and output at 96k, as well as on the analog output.

    When testing the 192k configuration, there were data on the same pins there also, but no analog.

    I have problem locating the pins for SCLK and FSCLK signals. Are they PGC0_CLKC_O and PGC0_FSC_O as seen in the SRU? If they are, they exist and for 192k config they are 24.575MHz and 192kHz respectively.However, no analog output.

    Update 2020-07-04:

    I measured the signals at the 74CBTLV3244 bus switch (according to the schematic), both at 96k and 192k.

    1A1 96k: 12MHz clock, 192k: 24MHz clock

    1A2 96k: 96k sync, 192k: 192k sync

    1A3 96k: data present, 192k: data present

    1A4 96k: quiet, 192k: quiet

    2A1 96k:12Mhz clock, 192k: 24MHz clock

    2A2 96k:96k sync, 192k:192k sync

    2A3: 96k: data, 192k: data

    2A4: 96k: quiet, 192k: quiet

    So the main signals are getting thru, but no analog out for 192k. Of course, there are more pins than these, but they are not as easy to find and measure.

    BN

  • I am now trying to study the signal routing of the Playback Demo. In the "ascii-graphic schematic" in the project Readme I can see that the main 25.47MHz clock is connected to DAI03, but there are no connections to DAI03 in the SRU. If I measure with oscilloscope, it is there.

    Could you please comment on this?

  • Hi BN,

    The master clock 24.576 Mhz is connected to ADAU1962A_CLKIN and available in DAI1_PIN03 also.

    You can refer ADSP-SC589 Example demo application project "SS_App_Core0" - system.svc - Signal Routing Unit - Routing details for how the master clock used in application FW.

    DAI1_PBEN03_I  - DAI1_LOW (To configure DAI1_PIN03 as Input pin)

    DAI1_CRS_PB03_O - PCG0_EXTCLKA_I  (Mater clock connected as external input to PCG A for generating I2S CLK and FS. The DAI PIN 3 and PIN 4 have cross connection option to get Signal to other DAI group pins and PCGs)

    DAI1_PB03_O - PCG0_EXTCLKC_I (Mater clock connected as external input to PCG C for generating TDM CLK and FS)

    There after the SCLK and FSCLK connected to other peripherals from respective PCG's.

    Thanks.

Reply
  • Hi BN,

    The master clock 24.576 Mhz is connected to ADAU1962A_CLKIN and available in DAI1_PIN03 also.

    You can refer ADSP-SC589 Example demo application project "SS_App_Core0" - system.svc - Signal Routing Unit - Routing details for how the master clock used in application FW.

    DAI1_PBEN03_I  - DAI1_LOW (To configure DAI1_PIN03 as Input pin)

    DAI1_CRS_PB03_O - PCG0_EXTCLKA_I  (Mater clock connected as external input to PCG A for generating I2S CLK and FS. The DAI PIN 3 and PIN 4 have cross connection option to get Signal to other DAI group pins and PCGs)

    DAI1_PB03_O - PCG0_EXTCLKC_I (Mater clock connected as external input to PCG C for generating TDM CLK and FS)

    There after the SCLK and FSCLK connected to other peripherals from respective PCG's.

    Thanks.

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