Building a 96k / 192k version of SS_App_Core for ADSP-SC58x EZ board

There is no example available with 96K or 192K sample rate. You need to modify the example demo application to 96K or 192K based on your requirement. Please refer the following information's how to modify the  example demo application,

1. The maximum clock range is 24.567MHz in ADSP-SC5xx EZ board, please refer corresponding EZ board harware schematic. You can find the EZ board harware schematic from "https://www.analog.com" by entering processor name as keyword in search. e.g. ADSP-SC589

The maximum Channels support are,

48K - TDM16

96K - TDM8

192K - TDM4

2. Modify the SigmaStudio schematic sampling rate to 96K or 192K. Modify the framwork configuration for the SPORT by considering maximum channel support possible with chosen FW sample rate.

3. Modify the number of channels support in FW application function AudioIoPcgInit() in file adi_ss_fw_audioIO.c

4. Modify the sample rate support and configurations of ADC and DAC with respect to sample rate. Go through the function adi_ss_system_initialize() in file adi_ss_app_system.c. The ADC and DAC configuration can be done by referring data sheet. You can find the datasheet from "">https://www.analog.com" by entering ADC or DAC name as keyword in search. e.g. ADAU1979 or ADAU1966A

5. You can verify the FW modification by running application in CCES debug session with build configuration as Debug.

6. If all configurations is fine then run application and download SigmaStudio schematic.

Thanks.

Thank you for the answer.

However, I will need more detailed support, since I have not touched these issues before, I need advice specifically on item 2. How is this done?

Moreover, in the file adi_ss_app_system.c, there is the following section:

    pSysConfig->eAdcSamplingRate = ADI_SS_SYS_SR_48000;
    pSysConfig->eDacSamplingRate = ADI_SS_SYS_SR_48000;

If I try to replace with 

    pSysConfig->eAdcSamplingRate = ADI_SS_SYS_SR_192000;
    pSysConfig->eDacSamplingRate = ADI_SS_SYS_SR_192000;

I find that this symbol is not defined.

BN

There is an older thread https://ez.analog.com/dsp/sigmadsp/f/q-a/67458/how-do-i-change-the-sample-rate-of-my-sigmastudio-system touching this issue in detail. However, it does not cover this hardware. It would be nice to see something similar for the ADSP-SC589 EZ board.

Thanks.

As I said earlier, ADSP-SC589 EZ-kit can support TDM4 for 4 ch with 192K sample rate, Please follow the steps to setup the Clock and channel configuration,

1. Demo application modify the number of channels from TDM8 to TDM4 in file adi_ss_fw_audioIO.c. refer the image.

2. In SigmaStudio framework configuration modify the Source 1 and Sink 1 SPORT settings as 

operation mode TDM4 and number of channels can be 4. The second source meant for I2S input from SPDIF source don't modify the settings. 

3. Change the schematic sample rate to 192K (Demo application uses this sample rate as I/O sample rate for configuring the clock )

4. rebuild the demo application, use the generated DXE's in SigmaStudio schematic and run the target with SigmaStudio.

I hope this changes work for 192K sample rate with demo application.

Thanks.

Thanks, I have already tested 1 and 3. without success.

However, the SigmaStudio framework config I have not done and I hope this will be the last piece in the puzzle.

Sakthi^vel said:

In SigmaStudio framework configuration modify the Source 1 and Sink 1 SPORT settings as 

operation mode TDM4 and number of channels can be 4.

Unfortunately, don't understand the above. Can you show it in a screen shot, like the one I posted?

During this long discussion, I came up with another question. In the QuickStart guide, the initial flashing process includes Core0.exe, Core1.dxe and Core2.dxe. How does this flashing relate to the Cores we now build for 192kHz? Should I flash again with the 192kHz Cores?

Please find the SigmaStudio SPORT settings,

Regarding Flash, you should generate LDR file with latest dxe's and flash again to target.

Please find some more modifications needs to be done on application framework ADC and DAC configuration,

1. DAC TDM4 configuration,

2. ADC TDM4 configuration,

The same way you need to check if we missed any ADC/DAC configurations for 192K.

Thanks.

Thanks for the news. However no luck yet.

I am now starting over.

I have removed and re-installed all software (CCES, SS, add-ins, etc.) just to be sure I have not accidentally damaged anything. I have re-flashed using the prebuilt Cores012 delivered with the installation, as described in the QuickStartGuide. I am testing the simplest possible 48k SS project (Analog input ports directly connected to output ports in the block schematics), and I notice one interesting thing:

When the FW configured as "dual core" everything works as expected, my oscilloscope shows output..

When the FW configured as "single core - Core 1" I get no output.

When the FW configured as "single core - Core 2" I get output sometimes, not consistent.

SPORTs and channels are default, TDM8 (SPORT4A 6 channels and SPORT 5A 8 channels)

This worries me for the 192k test, since the FW config seems not to be limited to only TDM4 and 4 channels, more things matter. What is the safest mode when testing 192k? Is it "dual core"?

What could be the reason for my single core problem when using the default 48k mode?

Can you recommend some reading for me to sort this out? I have been reading the docs delivered, but I have not yet found what I am looking for. The built-in SS help is empty, and links only to a web help, where some of the content is "under construction", a bit dated, and no entries for my ADSP-SC589 hardware.

I have now rebuilt the 192k cores according to your instructions, and flashed.

In my SS DualCore 192k project, I can see MIPS≈20 , so something is running, but I have no output.

If I want to debug the SS_App_Cores with CCES, should I flash the Debug versions instead of the Release?

You can run and debug application in CCES through ICE-1000 or ICE-2000 emulator mode with debug build configuration, also you can put break points in functions which you want to debug. All the variables can be viewed in debug session when stepping into the functions. Please follow the steps 1 to 17 in "AE_42_SS4G_QuickStartGuide.pdf" section "9.1 Steps to be followed to Debug a function in the schematic ".

If you want debug the application in flash, application should be build with debug configration and flashed to the target. The steps can be followed as above but you should select only "load symbols only" (step 14) option for all core dxe's while creating debug session. 
 

Sakthi,

As you may have noticed, I have put this issue aside for a while, I will try to solve the 192k issue later.

I will now try to solve the functional integration of my application to a standalone solution first.

This thread can be closed. Thanks for your support.

Sakthi,

As you may have noticed, I have put this issue aside for a while, I will try to solve the 192k issue later.

I will now try to solve the functional integration of my application to a standalone solution first.

This thread can be closed. Thanks for your support.