Building a 96k / 192k version of SS_App_Core for ADSP-SC58x EZ board

There is no example available with 96K or 192K sample rate. You need to modify the example demo application to 96K or 192K based on your requirement. Please refer the following information's how to modify the  example demo application,

1. The maximum clock range is 24.567MHz in ADSP-SC5xx EZ board, please refer corresponding EZ board harware schematic. You can find the EZ board harware schematic from "https://www.analog.com" by entering processor name as keyword in search. e.g. ADSP-SC589

The maximum Channels support are,

48K - TDM16

96K - TDM8

192K - TDM4

2. Modify the SigmaStudio schematic sampling rate to 96K or 192K. Modify the framwork configuration for the SPORT by considering maximum channel support possible with chosen FW sample rate.

3. Modify the number of channels support in FW application function AudioIoPcgInit() in file adi_ss_fw_audioIO.c

4. Modify the sample rate support and configurations of ADC and DAC with respect to sample rate. Go through the function adi_ss_system_initialize() in file adi_ss_app_system.c. The ADC and DAC configuration can be done by referring data sheet. You can find the datasheet from "">https://www.analog.com" by entering ADC or DAC name as keyword in search. e.g. ADAU1979 or ADAU1966A

5. You can verify the FW modification by running application in CCES debug session with build configuration as Debug.

6. If all configurations is fine then run application and download SigmaStudio schematic.

Thanks.

Thank you for the answer.

However, I will need more detailed support, since I have not touched these issues before, I need advice specifically on item 2. How is this done?

Moreover, in the file adi_ss_app_system.c, there is the following section:

    pSysConfig->eAdcSamplingRate = ADI_SS_SYS_SR_48000;
    pSysConfig->eDacSamplingRate = ADI_SS_SYS_SR_48000;

If I try to replace with 

    pSysConfig->eAdcSamplingRate = ADI_SS_SYS_SR_192000;
    pSysConfig->eDacSamplingRate = ADI_SS_SYS_SR_192000;

I find that this symbol is not defined.

BN

You can define macro for 96K or 192K sample rate how it is defined for 48K. You need to modify accordingly for following enum,

ADI_SS_SYS_SAMPLERATE

ADI_SS_SYS_ADC_SAMPLERATE

ADI_SS_SYS_DAC_SAMPLERATE

Note: You need to modify all other sample rate and channels related framework configurations for ADC and DAC.  

Not working. I have edited the .c and .h files where the 48k symbols were defined, and replaced by 192k equivalents.

The symbols for the 192k are not accepted.

Description Resource Path Location Type
Symbol 'ADI_SS_SYS_ADC_SR_192000' could not be resolved adi_ss_sys.c /SS_App_Core0/Source/Framework line 316 Semantic Error
Symbol 'ADI_SS_SYS_DAC_SR_192000' could not be resolved adi_ss_sys.c /SS_App_Core0/Source/Framework line 336 Semantic Error
Symbol 'ADI_SS_SYS_SR_192000' could not be resolved adi_ss_sys.c /SS_App_Core0/Source/Framework line 315 Semantic Error
Symbol 'ADI_SS_SYS_SR_192000' could not be resolved adi_ss_sys.c /SS_App_Core0/Source/Framework line 335 Semantic Error

If I temporarily edit e.g. ADI_SS_SYS_ADC_SR_192000 to ADI_SS_SYS_ADC_SR_48000 it becomes highlighted blue, right-click "open Decloaration" it opens my definition:

typedef enum ADI_SS_SYS_ADC_SAMPLERATE
{
	ADI_SS_SYS_ADC_SR_192000  = E_ADI_SS_SYS_ADC_SR_192000 /*!< Enum for sampling rate of 192000. */
}ADI_SS_SYS_ADC_SAMPLERATE;

Please explain what you mean by:

"Modify the SigmaStudio schematic sampling rate to 96K or 192K. Modify the framwork configuration for the SPORT by considering maximum channel support possible with chosen FW sample rate."

Also, please explain why I should refer to the schematic when I change the software.

I must say, you are very cryptic in your instructions. Please understand that I am very new to Analog Devices SHARC configuration and programming.

BN

Forgot to mention that it was possible to start the three programs in the debugger without any issues.

Which is surprising in itself considering the errors mentioned above.

BN

I have decided to put this SS_App_Core Demo project aside for a while since seems to be too complex for my current level. I will return to it when I feel I am ready for it.

Instead I will try the "adc_dac_playback" project, maybe it will give me some insights.

I am sure I will have questions there too, should I start a new thread for this?

BN

You need to modify the macro name also, please do the modifications as below,

1. adi_ss_sys.h

2. adi_ss_sys.h

3.adi_ss_app_system.c

4. adi_ss_sys_adc.h

5.adi_ss_sys_adc.h

6. adi_ss_sys_adc.c

7. adi_ss_sys_dac.h

8.adi_ss_sys_dac.h

9. adi_ss_sys_dac.c

10. adi_ss_sys.c

11.Re build the project

This changes may not work completely for 192K sample rate, you need to check for the significance of this sample rate variable and modify FW accordingly.

Thanks.

Thanks, I followed your instructions exactly, but I still get this:

Description Resource Path Location Type
Symbol 'ADI_SS_SYS_ADC_SR_192000' could not be resolved adi_ss_sys.c /SS_App_Core0/Source/Framework line 319 Semantic Error
Symbol 'ADI_SS_SYS_DAC_SR_192000' could not be resolved adi_ss_sys.c /SS_App_Core0/Source/Framework line 342 Semantic Error
Symbol 'ADI_SS_SYS_SR_192000' could not be resolved adi_ss_sys.c /SS_App_Core0/Source/Framework line 318 Semantic Error
Symbol 'ADI_SS_SYS_SR_192000' could not be resolved adi_ss_sys.c /SS_App_Core0/Source/Framework line 341 Semantic Error

Actually, I had already tried this before and got the same result. It is very strange, when I right-click/open Declaration on ADI_SS_SYS_SR_48000 ( which is blue and recognized) next to ADI_SS_SYS_SR_192000, I am taken to adi_ss_sys.h:

typedef enum ADI_SS_SYS_SAMPLERATE
{
    ADI_SS_SYS_SR_48000 = E_ADI_SS_SYS_SR_48000,
    ADI_SS_SYS_SR_192000 = E_ADI_SS_SYS_SR_192000
}ADI_SS_SYS_SAMPLERATE;

but the line defining ADI_SS_SYS_SR_192000 is apparently ignored.

Still not working, maybe I should install the previous version of CCES.

Still not working, maybe I should install the previous version of CCES.

I was able to modify the cces_playback project from 48k to 192k without too much difficulty. I was testing by running a square wave signal and judge the step response in oscilloscope, a big difference.

I suspect my SigmaStudio SS_App_Core project became corrupt in some way after my import to a local source copy, I will scrap it completely and try to import it again.

Final question for now: Is the order of the project path entries important?

I have imported the Demo SS_App_Core again, being very careful regarding the project path settings. Now the project builds without errors, but as soon as I open the source files adi_ss_app_sh0.c, adi_ss_app_sh1.c, adi_ss_app_system.c in the CCES editor window I get red "unresolved symbols" errors. 

I have made the suggested modifications in files:

adi_ss_sys.c, adi_ss_sys.h

adi_ss_app_system.c

adi_ss_sys_adc.c, adi_ss_sys_adc.h

adi_ss_sys_dac.c, adi_ss_sys_dac.h

and also in 

adi_ss_hal.c

Now please explain the meaning of "check for the significance of this sample rate variable and modify FW accordingly".

The project "ADC_DAC_Playback_SC589_SHARC_Core*" required only change of two lines to work at 192k. This playback project does NOT involve SigmaStudio. Is "modify FW accordingly" related to the SigmaStudio project settings?

In the SigmaStudio project, I set the executables for SHARC0 and SHARC1 to SS_App_Core1/Debug/SS_App_Core1.dxe and SS_App_Core2/Debug/SS_App_Core2.dxe respectively, no other settings are changed. The SigmaStudio project is set as DualCore. In the unmodified 48k version this works fine. If I compile and build the 192k debug version of the dxe in CCES (without errors) it STILL works at 48k in SigmaStudio. If I set the SigmaStudio project to use 192k I get no output.

This is the Firmware settings of my SigmaStudio project:

Is this appropriate for 192k sampling frequency?

There is an older thread https://ez.analog.com/dsp/sigmadsp/f/q-a/67458/how-do-i-change-the-sample-rate-of-my-sigmastudio-system touching this issue in detail. However, it does not cover this hardware. It would be nice to see something similar for the ADSP-SC589 EZ board.

Thanks.

As I said earlier, ADSP-SC589 EZ-kit can support TDM4 for 4 ch with 192K sample rate, Please follow the steps to setup the Clock and channel configuration,

1. Demo application modify the number of channels from TDM8 to TDM4 in file adi_ss_fw_audioIO.c. refer the image.

2. In SigmaStudio framework configuration modify the Source 1 and Sink 1 SPORT settings as 

operation mode TDM4 and number of channels can be 4. The second source meant for I2S input from SPDIF source don't modify the settings. 

3. Change the schematic sample rate to 192K (Demo application uses this sample rate as I/O sample rate for configuring the clock )

4. rebuild the demo application, use the generated DXE's in SigmaStudio schematic and run the target with SigmaStudio.

I hope this changes work for 192K sample rate with demo application.

Thanks.

Thanks, I have already tested 1 and 3. without success.

However, the SigmaStudio framework config I have not done and I hope this will be the last piece in the puzzle.

Sakthi^vel said:

In SigmaStudio framework configuration modify the Source 1 and Sink 1 SPORT settings as 

operation mode TDM4 and number of channels can be 4.

Unfortunately, don't understand the above. Can you show it in a screen shot, like the one I posted?

During this long discussion, I came up with another question. In the QuickStart guide, the initial flashing process includes Core0.exe, Core1.dxe and Core2.dxe. How does this flashing relate to the Cores we now build for 192kHz? Should I flash again with the 192kHz Cores?

Please find the SigmaStudio SPORT settings,

Regarding Flash, you should generate LDR file with latest dxe's and flash again to target.

Please find some more modifications needs to be done on application framework ADC and DAC configuration,

1. DAC TDM4 configuration,

2. ADC TDM4 configuration,

The same way you need to check if we missed any ADC/DAC configurations for 192K.

Thanks.

Thanks for the news. However no luck yet.

I am now starting over.

I have removed and re-installed all software (CCES, SS, add-ins, etc.) just to be sure I have not accidentally damaged anything. I have re-flashed using the prebuilt Cores012 delivered with the installation, as described in the QuickStartGuide. I am testing the simplest possible 48k SS project (Analog input ports directly connected to output ports in the block schematics), and I notice one interesting thing:

When the FW configured as "dual core" everything works as expected, my oscilloscope shows output..

When the FW configured as "single core - Core 1" I get no output.

When the FW configured as "single core - Core 2" I get output sometimes, not consistent.

SPORTs and channels are default, TDM8 (SPORT4A 6 channels and SPORT 5A 8 channels)

This worries me for the 192k test, since the FW config seems not to be limited to only TDM4 and 4 channels, more things matter. What is the safest mode when testing 192k? Is it "dual core"?

What could be the reason for my single core problem when using the default 48k mode?

Can you recommend some reading for me to sort this out? I have been reading the docs delivered, but I have not yet found what I am looking for. The built-in SS help is empty, and links only to a web help, where some of the content is "under construction", a bit dated, and no entries for my ADSP-SC589 hardware.

I have now rebuilt the 192k cores according to your instructions, and flashed.

In my SS DualCore 192k project, I can see MIPS≈20 , so something is running, but I have no output.

If I want to debug the SS_App_Cores with CCES, should I flash the Debug versions instead of the Release?