I want to Connect I2S input via SPORT0 Ports - Pins in use : 89 for FSCLK, 87 for BCLK and 32 for DATA
My input is Amanero384 - Pins in use : Data, FSCLK, BCLK
Using Demo DXE from SS4S 4.4
My Eval Board Is SC589 in Rev 2.1
On Demo DXE input doasn't work, when using SPDIF(COAX) via CD PLAYER it works well
When we swept pin 32 to 88 and after changed Serial Word Lenght to 16 - I heard some music with bit loss, on 24/32bit loud noise
Maybe somebody had the same issiue with Amanero device or can help with framweork config?
I"m using 0.1 wire directly from pins, lenght is 25cm
Thanks for help or some information.
There is one framework modification needs to done on ADSP-SC589 target application available in SS4S 4.4. The framework designed to demonstrate ADC 6ch TDM input from source 1 and 2ch I2S input from SPDIF(24-bit) source 2. The "SOURCE_SPDIF" macro used in SHARC cores to Left shift of data by 8 bits, so you are facing this issue. Please change the "SOURCE_SPDIF" macro value to 2 (one more than available sources by order 0,1,2) in file "adi_ss_fw_dataHandle_Sh.c", rebuild the application in Release configuration and verify your input/output.
Thanks Sakthi^v for you replay
There is our Framework config for Pins : 90 -FSCLK,, 91 - Data, 92 - BCLK From Amanero to SC589.
We also tried with SPORT0 on pins 87,88,89 but that was the same result.
Returning to SDP-BREAKOUT-BOARD MANUAL - PINs : 90-92 are Recive pins and 87-99 are Transmit - thats why we used SPORT1.
We also swept SOURCE_SPDIF from 1U to 2U.
Also have we warry about this errors? In other demos for ex SC573 - 0 errors
Cables have only 10cm from Amanero to Eval Board - Connector P1A.
We know that Amanero works in 100% But as input soruce we still have no source signal.
You need to configure corresponding ADSP-SC589 DAI pin's for I/O using "system.svc" setting of SRU routing in CCES project. Also you need to set pin buffer state to High if DAI pin is output and low for if DAI pin is input.
May I know which one is clock master ADSP-SC589 or your Amanero?
If ADSP-SC589 is clock master, BCLK and FSCLK DAI Pin as output pin by setting DAIx_PBxx_O and DAIx_PBENxx_I to DAIx_HIGH. Data pin as input by setting DAIx_PBxx_I and DAIx_PBENxx_I to DAIx_LOW state.
If Amanero is clock master, BCLK, FSCLK and Data pin as input by setting DAIx_PBxx_I and DAIx_PBENxx_I to DAIx_LOW state.
You will get proper signal's on the DAI pins to SPORT if above SRU configuration for DAI pin set properly in CCES application framework.
Also you need to set proper clock edges for both BCLK and FSCLK in SigmaStudio Framework configuration for the SPORT.
There is no problem with CCES error you have shown, please refer console window output for application framework related errors and warnings.