I am using ADSP-21479 EZ board and would like to bypass the on board codec and connect the DSP to digital input amplifier via the onboard expansion connector. Most of the DAIs if not all are available on this port so it should be possible. The SigmaStudio for SHARC has a default configuration mating the onboard codec which is not enough for my application. The SigmaStudio for SHARC User's Guide mentions that source code needs to be changed (and I'm assuming recompiled) in order to reconfigure audio IO. This sounds more complicated than it needs to be, but if this configuration is hard coded then is there any documentation on which files need to be changed. Are there any examples? Has anyone successfully done this?
Second question is related to SPORT capacity on ADSP-21479 and 21489. The DSP manual states there are 8 SPORTS on these parts. My application pushes me toward I2S connection instead of TDM (it is a hack and I prefer to keep the clk freq lower). My understanding is that each of the 8 ports has 2 data lines and each of the data lines in I2S mode can transmit two audio channels which equates to 4 audio channels per SPORT. This would mean 32 audio channels in I2S mode for the entire chip. This is sufficient for my application and I wanted to confirm if my understanding is correct.
The example demo application in SigmaStudio for SHARC package have all possible code that you are looking for PCG configuration, SPORT, SRU routing and DAI interface. You have to decide whether DSP as master or Codec as Master based on your requirements. The "enableOutputSPORT" called in application loop once when the data get processed and available for output. As you said the demo application is configured to support Analog with SPDIF Coexist audio mode. The "I2S_MODE" preprocessor macro can be added to project compiler setting to get "ANALOG_IN_ANALOG_OUT" audio mode support in demo application. Also the audio I/O modes can be modified in SigmaStudio schematic using "Input/Output" option by right click menu on "ADSP-214xx" IC. Refer the image .
Hello and thanks for the response.
I am not sure if I agree with your statement that demo app in the SS for SHARC package has all code needed for my application. The app has hardcoded dSP I/O pins which connect to AD1939 on board codec. It seems like it is specific to the EZ-BRD hardware and different I/O configuration has to be dealt with in code.
While I can reuse the ADC portion of AD1939, I cannot use its DAC portion. I will be using four external quad DACs each with its own CLK and FS signals to keep signal integrity in check (as explained above)
Because of the above I have to change the physical pin assignment and add new pin config not used in the demo app for the additional DACs and their clk/fs pins. I think that I will keep the ADC as master, but since DACs will use I2S interface then I will need to convert the TDM BCLK from ADC to I2S BCLK for DACs. I guess PCGA can be used for this.
The ADC FS signal can probably be assigned internally to all SPORTs in use to keep all signals in sync. I wonder if I need to pay attention to the BCLK delay caused by the BCLK freq reduction and if a special care needs to be taken to align BCLK with FS?