I am using ADSP-21479 EZ board and would like to bypass the on board codec and connect the DSP to digital input amplifier via the onboard expansion connector. Most of the DAIs if not all are available on this port so it should be possible. The SigmaStudio for SHARC has a default configuration mating the onboard codec which is not enough for my application. The SigmaStudio for SHARC User's Guide mentions that source code needs to be changed (and I'm assuming recompiled) in order to reconfigure audio IO. This sounds more complicated than it needs to be, but if this configuration is hard coded then is there any documentation on which files need to be changed. Are there any examples? Has anyone successfully done this?
Second question is related to SPORT capacity on ADSP-21479 and 21489. The DSP manual states there are 8 SPORTS on these parts. My application pushes me toward I2S connection instead of TDM (it is a hack and I prefer to keep the clk freq lower). My understanding is that each of the 8 ports has 2 data lines and each of the data lines in I2S mode can transmit two audio channels which equates to 4 audio channels per SPORT. This would mean 32 audio channels in I2S mode for the entire chip. This is sufficient for my application and I wanted to confirm if my understanding is correct.
Ans 1: There is no example for audio I/O reconfigure. we can get default framework related information's in "C:\Analog Devices\SoftwareModules\SigmaStudioForSHARC-SH-Rel2.2.0\Docs\SigmaStudio_for_SHARC_Framework.pdf" document. Also the EZ-Kit evaluation manual available in following link have hardware schematic information about DAI pins
Ans 2: Yes your understanding is correct. what about number of inputs and outputs? what about the Clock and FS source?
For example , Input Channel: 16 Output Channel:16 - we need 8+8 DAI ports for data line. If input/output have common source of Clock and FS we need only 2 DAI ports, otherwise we need extra DAI ports for each Clock and FS.
Thanks for your inputs.
I have been reading the Sharc Proc Hardware Reference and got some understanding about the port configuration.
I also tried to follow the code in app.c, initSRU_21469.c and initAudio.c located in adsp-21479-cces project which I believe is the application for the SigmaStudio for Sharc.
Here is my preliminary configuration. This only does the port configuration for 1 ADC 3 DAC related SPORTs (SPORT4 will be added). I am still missing the clock generation setup since I want the DSP to be the master and supply TDM CLK/FS to external ADC and I2S CLK/FS to external amplifiers.
Could you scan this and let me know if I am moving in the right direction.
Any help on clock configuration would be greatly appreciated.
// Config ADC to TDM mode
// Mic codec is slave
// Use SPORT1 for ADC data
SRU(HIGH, PBEN02_I); // Set DAI_P7 as output
SRU(HIGH, PBEN05_I); // Set DAI_P8 as output
SRU(SPORT0_CLK_O, DAI_PB05_I); // Route SPORT0 CLK to DAI_PB07
SRU(SPORT0_FS_O, DAI_PB02_I); // Route SPORT0 FS to DAI_PB08
SRU(DAI_PB01_O, SPORT0_DA_I); // Route ADC TDM data through DAI_P1 to SPORT0_DA_I
// Config DAC/PA in I2S mode (Assuming one SPORT can handle 4 audio channels (2 signals)
// PAs are slave
// Use SPORTs 2, 3, 4, 5
SRU(HIGH, PBEN09_I); // Set DAI_P9 as output
SRU(HIGH, PBEN10_I); // Set DAI_P10 as output
SRU(HIGH, PBEN11_I); // Set DAI_P11 as output
SRU(HIGH, PBEN12_I); // Set DAI_P12 as output
SRU(HIGH, PBEN13_I); // Set DAI_P13 as output
SRU(HIGH, PBEN14_I); // Set DAI_P14 as output
SRU(HIGH, PBEN15_I); // Set DAI_P15 as output
SRU(HIGH, PBEN16_I); // Set DAI_P16 as output
SRU(HIGH, PBEN17_I); // Set DAI_P17 as output
SRU(HIGH, PBEN18_I); // Set DAI_P18 as output
SRU(HIGH, PBEN19_I); // Set DAI_P19 as output
SRU(HIGH, PBEN20_I); // Set DAI_P20 as output
SRU(SPORT1_CLK_O, DAI_PB09_I); // Route SPORT1 CLK to DAI_P9
SRU(SPORT2_CLK_O, DAI_PB11_I); // Route SPORT2 CLK to DAI_P11
SRU(SPORT3_CLK_O, DAI_PB13_I); // Route SPORT3 CLK to DAI_P13
SRU(SPORT1_FS_O, DAI_PB15_I); // Route SPORT1 FS to DAI_P15
SRU(SPORT2_FS_O, DAI_PB17_I); // Route SPORT2 FS to DAI_P17
SRU(SPORT3_FS_O, DAI_PB19_I); // Route SPORT3 FS to DAI_P19
SRU(SPORT1_DA_O, DAI_PB10_I); // Route SPORT1 DATA A to DAI_PB10
SRU(SPORT1_DB_O, DAI_PB16_I); // Route SPORT1 DATA B to DAI_PB16
SRU(SPORT2_DA_O, DAI_PB12_I); // Route SPORT2 DATA A to DAI_PB12
SRU(SPORT2_DB_O, DAI_PB18_I); // Route SPORT2 DATA B to DAI_PB18
SRU(SPORT3_DA_O, DAI_PB14_I); // Route SPORT3 DATA A to DAI_PB14
SRU(SPORT3_DB_O, DAI_PB20_I); // Route SPORT3 DATA B to DAI_PB20
Hi,If you are going to use DSP as master then you can use PCG's for generating TDM and I2S clock for ADC's and DAC. Only 2 DAI pins needed for input BCLK and LRCLK to external ADC which is from PCG generating TDM clock, the same way 2 DAI pins needed for input BCLK and LRCLK to external DAC which is from PCG generating I2S clock. The PCG clock routing can be done like this,
//PCG clock and FS to DAI Pin for External ADC or DAC
SRU (HIGH, PBEN07_I);
SRU (PCG_CLKA_O, DAI_PB07_I);
SRU (HIGH, PBEN08_I);
SRU (PCG_FSA_O, DAI_PB08_I);
We can directly route PCG clock to SPORT for receiving data from/to ADC or DAC like below and no need of any DAI Pin's.
//PCG clock and FS to SPORT for External ADC or DAC inputsSRU (PCG_CLKA_O, SPORT3_CLK_I);SRU (PCG_FSA_O, SPORT3_FS_I);
The DAI pins needs to be assigned for data from/to ADC or DAC separately and that can be routed to SPORT input/output data line.
Please refer DSP clock section in hardware schematic available in evaluation kit manuals for making DSP as master.
Thanks for the detailed reply!
I have used dedicated pins for BCLK and LRCLK because this system will be built out of eval boards and clock connections will be relatively long. Having dedicated clock pins and point-to-point connections should improve signal integrity.
I do still have several open questions related to PCG/SPORT config which hopefully will get cleared away once I finish reading the PCG chapter in the SHARC Hardware Reference.
Finally I am debating on whether I should keep DSP as master. I think in most designs with relatively simple clock scheme the ADC is a master and clocks flow alongside with the signal flow. In this case I think I would not need to touch PCG, but just connect the ADC SPORT clocks with all DAC SPORT clocks and all data should stay in sync. I am curious about your opinion on this. In my case the audio will always come from ADC so this approach makes sense and I think makes things simpler.
I identified functions in the SigmaStudio for SHARC app project which I think need to change in order to change SPORTs to my configuration (1 input SPORT(no change) and 4 output SPORTs --> 16 audio output channels)
void InitDAI_ANALOG_SPDIF_Coexist(tAppInfo *pAppInfo, int nOutputSamplingFreq) located in initSRU_21469.c
void ConfigureSportTDM(tAppInfo *pAppInfo, int SportTCBSize) located in initSPORT.c
but also change and add funciton to configure SPORTs for I2S external DACs
void ConfigureSportI2S(tAppInfo *pAppInfo, int SportTCBSize)
void enableOutputSPORT(int bFlag,int I2SorTDM,int nOutSamplingFreq) which surprisingly is located in the application loop for(;;), There is an if statement which enables it just once... but I failed to understand why this cannot be called prior to entertaining the forever loop.
I think I do need to add ISR for the new SPORTs which are not used in the default app. any suggestions?
There are also several audio configurations passed from the Host app to this Target app which decide if SPDIF is used or analog only audio inputs or both SPDIF and analog. As i traced the code it seems that only the Analog with SPDIF Coexist option has been implemented. Could you confirm?
I would prefer to modify the Analog only option which is the simplest and also because I will most likely use the internal Codec for input and will not use SPDIF I/O for sure.
The example demo application in SigmaStudio for SHARC package have all possible code that you are looking for PCG configuration, SPORT, SRU routing and DAI interface. You have to decide whether DSP as master or Codec as Master based on your requirements. The "enableOutputSPORT" called in application loop once when the data get processed and available for output. As you said the demo application is configured to support Analog with SPDIF Coexist audio mode. The "I2S_MODE" preprocessor macro can be added to project compiler setting to get "ANALOG_IN_ANALOG_OUT" audio mode support in demo application. Also the audio I/O modes can be modified in SigmaStudio schematic using "Input/Output" option by right click menu on "ADSP-214xx" IC. Refer the image .
Hello and thanks for the response.
I am not sure if I agree with your statement that demo app in the SS for SHARC package has all code needed for my application. The app has hardcoded dSP I/O pins which connect to AD1939 on board codec. It seems like it is specific to the EZ-BRD hardware and different I/O configuration has to be dealt with in code.
While I can reuse the ADC portion of AD1939, I cannot use its DAC portion. I will be using four external quad DACs each with its own CLK and FS signals to keep signal integrity in check (as explained above)
Because of the above I have to change the physical pin assignment and add new pin config not used in the demo app for the additional DACs and their clk/fs pins. I think that I will keep the ADC as master, but since DACs will use I2S interface then I will need to convert the TDM BCLK from ADC to I2S BCLK for DACs. I guess PCGA can be used for this.
The ADC FS signal can probably be assigned internally to all SPORTs in use to keep all signals in sync. I wonder if I need to pay attention to the BCLK delay caused by the BCLK freq reduction and if a special care needs to be taken to align BCLK with FS?