As I understand the framework buffer ( default 64 ) contributes the major latency due to DSP measured between Analog In and Analog Out. To reduce the buffer size in application and Sigma
Studio can reduce the latency significantly ( e.g. 64 -> 32 ) if the overall system performance can be still kept. So what we found is that the latency is almost same when we build a schematic in
block based or sample based because the latency of framework buffer is same and contribute the major part of latency. Here below are my questions :
1. The buffer size cannot be reduced below in Sigma Studio ( Ver 3.14 Build 2 ). So the demo application can only use 8 as minimum buffer size . It causes the latency from framework buffer still , cannot help to reduce the latency further even the sample based schematic is used. Is my understanding correct ?
2. What is the advantage of using sample based schematic over block based ? or vice versa in Sigma Studio
May I know which version of SigmaStudio for SHARC package and target platform you are using?
Ans 1: Yes your understanding is correct, you can't reduce buffer size less than 8.
Ans 2: We need to use block based processing for reduced MIPS usage, the reasons are,
> Target framework MIPS is less for higher buffer size because of ISR
> SigmaStduio processing MIPS is less for higher buffer size because reduced function call overhead and stalls
> Available MIPS for our audio processing is high based on above two points
Thanks for your prompt reply and sorry for my late response. We are using ADSP21489 , SigmaStudio for SHARC Rel 2.2.0
It make sense to use a higher buffer size to reduce the demand of MIPS but it will add latency between Analog In and Analog Out.
As the minimize buffer size is 8 in Sigma Studio , it means no matter block schematic or sample schematic are being used, the overall latency in one DSP cannot be reduced further , it will be at least ~0.3 ms (@48K sampling rate ) even there is enough MIPS to process sample by sample without requirement of buffering.
Is my understanding correct ?
Yes, your understanding is correct. The minimum buffer size is kept 8 for SIMD and optimization purposes.
As you said the latency with buffer size 8 is 333 usec and its very small latency.
Are you looking for further reduction in the I/O latency? May I know what's your minimum latency requirement and for which application?
Your reply will help us to understand your need and we will let you know if any way we can help you.
Comparing different Mixing Console specification in the market, there are usually 2 DSPs, one for IN Processing and one for OUT Processing. The requirement of latency ( Analog In to Analog Out ) has to be as less as possible , common acceptable value is ranging from 0.8ms to 1.x ms .
By roughly calculation , the ADC and DAC will contribute around 0.5 ms , if a ADSP21489 without any processing units ( i.e. directly connect Schematic Input to Output ) with buffer size 8 has at least 0.3ms , the latency of this path ADC --> DSP#1 --> DSP#2 ---> DAC will be at least 1.1 ms or more .
After some test to build a block schematic with 20 channels and each channel includes some processing units ( e.g. compressor, PEQ , HPF ...) , it seems it is not possible to set buffer size as small as 8 , it must be increase the buffer size to a bigger value. If so, it is not very easy to achieve the overall latency to be 1.x ms especially MCU needs to keep communication with 21489 to frequently read back the signal level of each channel. It will increase the MIPS usage further.
Please let me know if there is any better way to optimize the Sigma Studio to be minimize the overall latency as much as possible.
There are some parameters can be adjusted in Demo application framework (C:\Analog Devices\SoftwareModules\SigmaStudioForSHARC-SH-Rel2.2.0\Target\Demo\ADSP-21489) to reduce the latency.
1. PROCESSING_BLK_SIZE and SPORT_BUFFER_SIZE(app.h) can be reduced to 8 if you set SigmaStudio block processing buffer size to 8.
2. nFirstTimeFl and nFirstTimeSPDIFFl (app.c) can be reduced to 1 if input/output sample rates are same.