Latency and Block Size in Sigma Studio

Hi Team, 

       As I understand the framework buffer ( default 64 ) contributes the major latency due to DSP measured between Analog In and Analog Out.  To reduce the buffer size in application and Sigma

Studio can reduce the latency significantly ( e.g. 64 -> 32 )  if the overall system performance can be still kept.   So what we found is that the latency is almost same when we build a schematic in

block based or sample based because the latency of framework buffer is same and contribute the major part of latency.   Here below are my questions : 

1. The buffer size cannot be reduced below  in Sigma Studio ( Ver 3.14 Build 2 ).   So the demo application can only use 8 as minimum buffer size .  It causes the latency from framework buffer still ,  cannot help to reduce the latency further even the sample based schematic is used.   Is my understanding correct ?  

2. What is the advantage of using sample based schematic over block based ?  or vice versa  in Sigma Studio