I need help because I'm trying to obatin a long delay line of up 20 SEC on my ADSP21489 EZ-KIT LITE using external SDRAM.
I've followed the istruction reported on post
- I've increased the #define MAX_DELAY_IN_MSEC (20000) on adi_ext_OffchipDelay.h
- I've modified the adi_OffchipDelay_ExtPort.ssg and recompiled the OffChipDelayExtPortND.dll using different name
in the way that I can distinghish my new module on SigmaStudio
- I've recompiled a CCES loader using SDRAM external memory and adding a buffer for my own external memory delay line
After the compilation the buffer is allocated at the address 0x900000 as I can read on adsp-21489-CCES.map.xml :
<INPUT_SECTION id='04960EF0' name='seg_pmda' start_address='0x900000' size='0x100000' element_at='0x0' ><INPUT_FILE><![CDATA[Source\app.doj]]></INPUT_FILE><SYMBOL name='_happyDelayLine' address='0x900000' size='0x100000' binding='GLOBAL'><DEMANGLED_NAME><![CDATA[happyDelayLine]]></DEMANGLED_NAME></SYMBOL></INPUT_SECTION>
I've created a simple test project on SigmaStudio using my new module and use the correct address allocated 0x900000
It work but have a strange behavior:
- until the ms delay stay under the 120ms it work
- over the 120ms the delay obtained cycles from 1 to 120ms for example setting 122ms I obtain 2msec of delay
- for large number like 10000 it stop to work and the LED7 on the evaluation board is ON
It seems that somewhere the DMA controller on the SHARC works using standard 120ms MAX delay.
Can anyone help me?
did you generated DLM after "MAX_DELAY_IN_MSEC" modification?
Please refer "SigmaStudio_for_SHARC_AlgorithmDesigner.pdf" document from "C:\Analog Devices\SoftwareModules\SigmaStudioForSHARC-SH-Rel2.2.0\Docs" and section "8.1 Steps to Rebuild the Example Plug-Ins".