Long delay line in SHARC ADSP21489

Hello.

I need help because I'm trying to obatin a long delay line of up 20 SEC on my ADSP21489 EZ-KIT LITE using external SDRAM.

I've followed the istruction reported on post

https://ez.analog.com/dsp/software-and-development-tools/sigmastudio-for-sharc/f/q-a/86395/off-chip-delay-external-port

- I've increased the             #define MAX_DELAY_IN_MSEC   (20000)           on adi_ext_OffchipDelay.h 

- I've modified the    adi_OffchipDelay_ExtPort.ssg     and recompiled the     OffChipDelayExtPortND.dll     using different name

  in the way that I can distinghish my new module on SigmaStudio

- I've recompiled a CCES loader using SDRAM external memory and adding a buffer for my own external memory delay line

After the compilation the buffer is allocated at the address 0x900000 as I can read on      adsp-21489-CCES.map.xml :

<INPUT_SECTION id='04960EF0' name='seg_pmda' start_address='0x900000' size='0x100000' element_at='0x0' >
<INPUT_FILE><![CDATA[Source\app.doj]]></INPUT_FILE>
<SYMBOL name='_happyDelayLine' address='0x900000' size='0x100000' binding='GLOBAL'><DEMANGLED_NAME><![CDATA[happyDelayLine]]></DEMANGLED_NAME></SYMBOL>
</INPUT_SECTION>

I've created a simple test project  on SigmaStudio using my new module and use the correct address allocated 0x900000 

So...

It work but have a strange behavior:

- until the ms delay stay under the 120ms it work

- over the 120ms the delay obtained cycles from 1 to 120ms for example setting 122ms I obtain 2msec of delay

- for large number like 10000 it stop to work and the LED7 on the evaluation board is ON

It seems that somewhere the DMA controller on the SHARC works using standard 120ms MAX delay.

Can anyone help me?

Best regards

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  • Hello.

    I've restarted to work on this application but I still have problems.

    At this point I'm able to

    - rebuilt using CCES the .dyn file with the #define MAX_DELAY_IN_MSEC enhanced to 1000 msec

    - modify the .ssg project for accept this max param value and generate the new .dll included on SS

    - use on a SS project this module that work fine up to 1000 msec

    Note that I'm using in CCES app.c a buffer 

    float32_t pm happyDelayLine[57671679];

    that is located on external sdram as you can notice on map.xml

    <MEMORY id='02C66A10' name='mem_sdram_pmda' start_address='0x900000' end_address='0x3ffffff' type='DM' qualifier='RAM' externalqualifier='' width='0x10' words_used='0x36fffff' words_unused='0x1' >
    <OUTPUT_SECTIONS>
    <OUTPUT_SECTION name='dxe_sdram_pm_data' id='18F0F230' memory_id='02C66A10' type='SHT_NOBITS' start_address='0x900000' word_size='0x36fffff' word_size_unmapped='0x0' word_size_reserved='0x0' >
    <INPUT_SECTIONS>
    <INPUT_SECTION id='18C4E8E0' name='seg_pmda' start_address='0x900000' size='0x36fffff' element_at='0x0' >
    <INPUT_FILE><![CDATA[Source\app.doj]]></INPUT_FILE>
    <SYMBOL name='_happyDelayLine' address='0x900000' size='0x36fffff' binding='GLOBAL'><DEMANGLED_NAME><![CDATA[happyDelayLine]]></DEMANGLED_NAME></SYMBOL>
    </INPUT_SECTION>
    </INPUT_SECTIONS>
    </OUTPUT_SECTION>
    </OUTPUT_SECTIONS>
    </MEMORY>

    But...

    If I try to enlarge the  MAX_DELAY_IN_MSEC  to 2000 msec and repeat the above procedure, it happens a strange behaviour:

     the delay is fragmented in 3 block in the mean that I hear a partial signal repetition on

    - the first at 0,7 sec

    - the second at 1,2 sec

    - the third at 2 sec or above

    What's the problem?

    I have a mistake on the source code of the SS delay module?

    There is a faulty management of DMA memory for the circular buffer?

    Or the problem is the buffer on app.c application?

    The source code is the adi_ext_OffchipDelay!

    Thanks in advance for the support.

  • Sorry for my last post...I have understand my error!

    I set a wrong address in the box because the value is in decimal and not in hex format.

    The module work in correct way.

    Thanks