Q&A - Recent Threads

EMAC for ADIN1300

chb613 — Tue, 31 Mar 2026 05:02:56 GMT

Hi,

I am using SC589-MINI and I want to test ADIN1300 PHY.There is no relevant driver code in the CCES3.0.2,could you provide the ASIN1300 driver code? And please tell me how to add the driver code to the CCES.

Regards,

Bingo

Wrong post

TonyTsou — Mon, 19 Jan 2026 11:30:22 GMT

Wrong post@

2-way crossover CCES project set up

AntonLo — Mon, 24 Nov 2025 14:32:11 GMT

Hi, I‘m working with the ADZS-SC589-MINI at the moment but I‘m relatively new to all of this. I learned C/C++ at university but I’m no expert by any means. For now I would like to implement a simple 2-way crossover using CCES. As far as I understood you write all the relevant code for this in the callback_audio_processing.cpp file, then build and debug, which is what I did. However all I got was regular playback on both channels with very reduced volume.
I understand that you can’t review all my code here until it works but I would just like to ask if there are any fundamental things I need to change or set up before using the SC589 board for this application? To me it sounded easy to do in theory but I might’ve underestimated the complexity. And that’s what I want to find out before finding other easier solutions.

Debugging with breakpoints and expressions

TeylorW — Thu, 24 Jul 2025 17:26:21 GMT

Hello,

I am trying to debug some effect modules I have made using the built-in ADI modules as a reference. For now, I am attempting to set breakpoints and step through the built-in source files to see what I should be expecting. I have a few questions regarding the debug session. Note that all my modification to the ADI source files I mention below are working, the debugging is the only confusing part here.

1. When setting hardware breakpoints in for example effect_stereo_flanger.c core 1 inside of the read function, the program breaks at the same line, but in core2. This is confusing since the flanger is handled in core1.... Now for core2. I rearranged the core2 processing within audio_effects_selector.cpp so that it works exactly how core 1 works. I tried setting hardware breakpoints in the effect_stereo_reverb.c source file in both cores, but neither are breaking the program. Curious how I should be setting breakpoints so that I can debug for each core. I've tried clicking on core1 in the debug tree to direct debugging to core 1, but that did not make a difference. Some of the breakpoints I have made show up in the picture here:

2. All of the ADI effect modules have code that is helpful for debugging. An example of that is the result enumerations. What is the easiest way to use the expression tool in the debugger to view the enum return results of functions.

I am new to the SHARC core architecture and am having a tough time wrapping my head around all this. I appreciate your time and patience.

Thanks,

Teylor

Running framework demo - cannot start Core2 in Debug

AnaDoug — Thu, 26 Jun 2025 13:09:41 GMT

Hi Folks,

I'm newly using the SHARC Audio Module (bare, no fins), ICE-1000, Windows 11 and CCES 3.0.2, with the ADI_SAM_BareMetal_SDK-Rel2.2.0 BareMetal Framework example code.

I load the example project from the framework directory, and get the 3 cores into CCES, and compile it.

I created a run & debug session for the ICE-1000 emulator.

I can download the whole application to the SAM without debugging, and the app starts, and the 3 LEDs blink as expected. I see UART output on my computer.

However, if using the default debug configuration, if I download the application, it properly hits the main() breakpoint in each core, and nothing happens.

The CCES UI shows me the breakpoints at the top of main() for both Core0 (in startup_code_core0.c) and Core1 (startup_code_core1.cpp). I am able to then hit F5/Resume to get those cores to run. The Arm core starts blinking its light. The SHARC+ Core1 starts outputting messages to UART, but not blinking it's light (which it needs to talk to Core2 to do).

My big problem: CCES at no point gives me any way to see the breakpoint status of SHARC+ Core2, nor to resume it, so I can't properly debug the SAM because I can't start or step through Core2. All CCES does is show me the two files for Cores 0 and 1, and does not give me any way to see Core 2 nor resume it from it's default main breakpoint.

Does anyone know why CCES is not showing me the breakpoint of Core2?

Just to make sure it's actually breaking Core 2, I created a new debug configuration and turned off the default main() breakpoints for all 3 cores and the debugged version of execution does the same thing as the non-debugged version.

Please help? Thanks!

Buffers and memory allocation on sam board

TeylorW — Mon, 16 Jun 2025 22:45:51 GMT

Hello,

I have a few questions regarding memory allocation and buffers. Bear in mind I'm new to this processor and to DSP development in general. It is my understanding that if I want to access the external DDR ram on the sam board, then should use the #pragma directive. For example if I want to store a digital delay buffer in ddr ram I would write:

#pragma section("seg_sdram")

float digital_delay_buffer[DIGITAL_DELAY_BUF_SIZE];

#pragma section()

Questions:

- If I want to store in L1 or L2, what is the directive for those? Is there a file... maybe the .ldf where I can find this information? Where can I find the .ldf file and any relevant file I need.

- If I set the buffer size for a delay for example to 2^18 (is it recommended to have buffers of base-2 size?), Max delay time = BUF_SIZE / Sampling rate(48k) = 5.46 seconds, memory usage = 2^18 * 4(because float is 4 bytes per) = 1,048,576 bytes ~1MB. Because of all the space this takes up, it is recommended to use the external ram to store it. But if I have other effects in series with this that don't require a large buffer, should I be using a separate buffer? If so, how can I cascade the audio signal so that it is processed by each effect it goes through.

- Is there any documentation regarding memory allocation on the SHARC processors or even for the sam board specifically?

Building example makefile project.

JSlotaJpe — Fri, 23 May 2025 04:48:44 GMT

How can i build this starter project using makefiles in CrossCore Embedded Studio? Is there any guide?

github.com/.../sam-audio-starter

Importing it as C/C++ makefile project is not possible as CrossCore overwrittes makefile's shell to use window's one.
Is there any tested/verified guide to accomplish it?

Debugging Analog Devices audio starter

JSlotaJpe — Thu, 22 May 2025 08:38:06 GMT

I bought SHARC Audio Module (ADZS-SC589-MINI) from Analog Devices to setup a networking project, got cross core studio and downloaded sample advanced project from there:

github.com/.../sam-audio-starter

I found that i can build this exemplary project using makefile as mentioned in description, generated binaries for arm and sharc core - no problems here so far.

Then i tried to create debug configuration in crosscore using generated binaries as mentioned in the guide but i can't force cross core embedded studio to stop at given breakpoint, meaning i can go line by line using step but whenever i press the run button it will not stop at any breakpoint.

Does anyone of you maybe encountered such issue? What would be your approach to fix it/go around it. Breakpoints would be really helpful with networking apps as it's difficult to catch errors with asynchronous operations.

I already checked the makefile, im certain that it's debug build, flashed it and tried multiple combinations of configuration options in cross core but with no success.

Example source codes were not executing

ppl — Tue, 13 May 2025 07:21:28 GMT

Hi,

I am currently working with the ADSP-SC589 MINI Evaluation Board and have downloaded several example projects from CCES 3.0.2. These examples compile successfully without any errors. However, when I attempt to debug them, I encounter the same issue across all examples—the code gets stuck in a specific loop, as shown in the attached image.

I would appreciate any guidance you can provide to help resolve this issue.

Thank you in advance!

SHARC vs Sigma DSP in MIPS

EricSa — Mon, 07 Apr 2025 08:58:07 GMT

Hello together,

maybe the question is stupid but I cant find the correct informations. We are always using Sigma DSPs especially the ADAU1467 in our projects which has 6144 MIPS. In almost all of our products we reach the limit of the instructions, so we evaluate to switch to SHARC for bigger projects. Is there any "easy" comparison in terms of MIPS between SHARC and Sigma DSPs? We are interessted in the ADSP-SC573 and ADSP-SC570.

ADAU1467	ADSP-SC573	ADSP-SC570
6144	?	?

For sure this is not a precise comparison but we just want to get an impression how much "more" we can do with a SHARC.

Thanks all of you in advance,

Eric

MIDI Synthesizer No Sound Despite MIDI Input (SC589)

Nurmukhammad — Thu, 03 Apr 2025 19:38:41 GMT

Hi all,

I’m currently working on a project using the SHARC Audio Module (ADSP-SC589) and following the MIDI synthesizer tutorial:

Tutorial: A Simple MIDI Synthesizer

MIDI Sawtooth Synth (Core 1)

MIDI Virtual Analog Synth (Core1) / Effects (Core 2)

I’ve compiled and loaded all the code demonstrated in simple MIDI tutorial and the Faust-generated synthesizer, and connected a MIDI keyboard to the board’s MIDI input. The MIDI IN LED on the board blinks correctly when I press keys, confirming that the board is receiving data.

However, no audio is coming out of the speakers, and I can’t hear any response from the synth.

Any idea on how can I resolve this problem?

Thank you in advance!

A2B interface, slave

DavAdr — Wed, 12 Feb 2025 14:29:44 GMT

We are trying to connect two Shark modules, but the slave isn't working (the problem starts when we change the value TRUE which makes that the program works as a MASTER for a FALSE value). The program stops at some point and doesn't charge on the Shark module. We followed the code from the Analog Wiki to establish the connection.

reading from A2B bus connected to RNC sensors

laala — Wed, 11 Dec 2024 09:58:14 GMT

Hi,

I am using the SAM (ADZS-SC589-MINI) evaluation board, which is connected to 7 Molex RNC sensors via the A2B bus. The board is also connected to a Raspberry Pi 4B through a USB port, allowing me to read sensor data using a Python script. The board has been configured using SigmaStudio. However, I am encountering an issue: when the sensors are in a stationary position, I expect to receive readings of [0, -1, 0] for each sensor. Instead, I receive different values that repeat continuously. Could you please help me identify and resolve this issue? Thank you in advance!

[ 0.146 -0.326 0. ]
parsed_data: [-0.09 -0.798 -0.268]
parsed_data: [ 0.146 -0.798 -0.268]
parsed_data: [-0.326 -0.798 -0.268]
parsed_data: [ 0.146 -0.798 -0.536]
parsed_data: [-0.09 -0.798 0. ]
parsed_data: [-0.09 -0.562 -0.268]
parsed_data: [-0.326 -0.798 -0.536]
parsed_data: [-0.09 -0.798 0. ]
parsed_data: [-0.09 -0.562 0. ]
parsed_data: [ 0.146 -1.034 -0.268]
parsed_data: [-0.09 -0.562 -0.536]
parsed_data: [-0.09 -0.562 -0.268]
parsed_data: [-0.326 -0.562 0. ]
parsed_data: [ 0.146 -0.798 0. ]
parsed_data: [ 0.146 -0.798 -0.268]
parsed_data: [ 0.146 -0.798 -0.536]
parsed_data: [-0.09 -0.326 -0.268]
parsed_data: [-0.09 -0.798 -0.268]
parsed_data: [ 0.146 -0.562 -0.268]
parsed_data: [-0.09 -0.798 -0.536]
parsed_data: [-0.09 -0.562 -0.536]
parsed_data: [ 0.146 -0.798 -0.268]
parsed_data: [ 0.146 -0.798 -0.268]
parsed_data: [-0.09 -0.562 0. ]
parsed_data: [-0.09 -0.326 -0.536]
parsed_data: [-0.09 -0.798 -0.268]
parsed_data: [-0.09 -0.798 -0.268]
parsed_data: [ 0.146 -0.798 -0.536]
parsed_data: [-0.09 -0.798 -0.268]
parsed_data: [ 0.146 -0.798 0. ]
parsed_data: [-0.09 -0.798 -0.268]
parsed_data: [-0.09 -0.562 0. ]
parsed_data: [-0.09 -0.798 0. ]
parsed_data: [-0.09 -0.562 -0.268]
parsed_data: [ 0.146 -0.798 -0.268]
parsed_data: [-0.326 -0.562 -0.536]
parsed_data: [-0.09 -0.798 -0.536]
parsed_data: [ 0.146 -0.562 -0.268]
parsed_data: [-0.09 -0.562 -0.536]
parsed_data: [ 0.146 -0.798 0. ]
parsed_data: [-0.09 -1.034 -0.268]
parsed_data: [-0.09 -0.798 0. ]
parsed_data: [-0.09 -1.034 -0.536]
parsed_data: [ 0.146 -0.798 -0.268]
parsed_data: [-0.09 -0.798 -0.268]
parsed_data: [-0.326 -0.798 -0.268]
parsed_data: [-0.09 -0.798 -0.268]

About Ethernet connection using SAM (ADZS-SC589-MINI) evaluation board

HTCV3 — Fri, 29 Nov 2024 08:58:18 GMT

Hi,

We are using SAM (ADZS-SC589-MINI) evaluation board to confirm Ethernet connection.
We are following the instructions on SAM wiki, but we are unable to switch COM port settings as described on wiki.
　　wiki.analog.com/.../examples-ethernet-audio

Could you please tell us a few things that concern you?

(1) What CCES sample project should I use to confirm?
　 Do I need to get the sample project from SRF?
　 Currently we are trying to start a project in SAM_BareMetal_SDK-Rel2.1.2 framework.

(2) When setting the IP address, it says to execute the syslog command, but I don't know how to confirm this.
　 Please tell me in detail how to confirm.

(3) When I start Tera Term and check COM port settings, only a normal COM port is visible.
　 The port labeled SC5xx Communications Port as described on wiki is not displayed.
　 Please tell me how to set it so that the port labeled SC5xx Communications Port is displayed.

Development environment being checked:
・ADZS-SC589-MINI(Rev1.5)
・CCES 3.0.2
・ICE-1000(1.2)
・SAM_BareMetal_SDK-Rel2.1.2 framework

Best regards.

How to use external memory on the sam board.

thopman — Mon, 04 Nov 2024 11:50:22 GMT

Are there any examples that show how to assign parts of the code to the different ram segments available on the sharc audio module. I tried looking for examples and or ee notes but i could not find any. i'm particularly interested in the use of the external memory. I'm currently using the bare metal framework which afaik sets up the app.ldf with external memory. I'm quite new to sharc programming so i'm having some difficulty locating the appropriate documentation. I tried finding the info in the sharc compiler manual (only version 2.9 is available online) but it goes into so much detail that it's hard to find the exact info i need. A little bit of background: i'm working on getting the latest faust release working with cces 3.0.1. I have code that compiles but is too large for the default memory settings.

Included ICE-1000 emulator

AnonymUser — Sat, 13 Jul 2024 15:55:02 GMT

Hi,

I'd like to purchase the SC589 audio development kit and I wanted to know if the ICE-1000 emulator can then be reused to target other DSPs in the SHARC family if needed(BGA assembly no available/extra cost,better price/part etc.)(the 176LQFP ADSP-21571 will be the actual DSP used on the custom prototype) provided I already have a full license for CCES?

Also how portable is the code for SC589 across the family?

From what I managed to look at and read in the HW manuals ,those parts are quite similar (excluding the Cortex-A5,frequency range of core clock).

Can I port an audio firmware designed for SC589 to ADSP-21571 easily ?

My goal for now is to have some basic crossover(Linkwitz-Riley) working using the IIR/FIR accelerators and move from there.

Thank you.

How to mute the Audio line out port?

emi.rein — Tue, 28 May 2024 06:37:32 GMT

Hi,

I would like to mute the audio port (for some time) on the SC589-MINI during running my app. How should I do that?

Regards,

Reinier

Ethernet support for Baremetal Framework?

Tom6666 — Fri, 24 May 2024 16:13:11 GMT

Hi all,

for my current project it would be quite handy to send over some UDP commands between PC and the SHARC Audio Module. My project is based on the Baremetal Framework, so switching to SAM audio starter would cause extra work that I would prefer to avoid.

Is it possible to add Ethernet support to the Baremetal Framework? Is there even some code available for this purpose?

Cheers,

Tom

SAM Board not entering DMA ISR

issac — Wed, 01 May 2024 02:37:24 GMT

I'm trying to run the SAM Bare Metal Project (V2.2) on my V1.4 SAM board. It's currently unaltered from the default program, other than "SHARC_SAM_REV_1_3_OR_LATER" being set to TRUE in the audio_system_config.

When I attempt to debug the program with the ICE-1000, the program get's stuck when enabling the DMA's. The error logging prints 'Starting audio DMA's' on both cores, but never reaches the "Audio DMA is running" stage. It instead stays here in the startup code

while (!multicore_data->sharc_core1_processing_audio)
continue;

I can see from the register window that the DMA's are configured and enabled, but they never enter their ISR's (and update the mutlicore_data structure to progress past this point). I am also getting a very similar issue in my own simple project. Any advice would be greatly appreciated.

For reference:

CCES: 2.9.4 (although also testing on 2.12.0 and 3.0.0)

BM Framework: 2.2

SAM Board: 1.4

Thanks in advance!

Secure boot in SC589 SAM board

Oharachild — Wed, 27 Mar 2024 15:30:13 GMT

Hi,

I'm using SC589 SAM BOARD for my Project.Im facing a pbm in SPI flash boot.

I'm intended to use for secure booting.Im just following the EE366 but Simple LED Flash boot itself is not working.

- 1. First, I have modified led_blink as per SAM board which I got from SECURE Boot example of SC589 application note And it's working for me in debug mode. But in booting it's not working.

Ldr generation: Driver file added from SAM BSP, init file not included,Jumper 1&2 connected, SPI flash,bin,01.

Please give a solution for this.

2. Is sc589 mini supports secure boot?

Thanks

ADSP SC589 VPX

paramasivanvelu — Tue, 26 Mar 2024 10:48:50 GMT

hello guys.

I am new to this VPX Technology. I Need some software References and Idea for VPX integration with ADSP SC589. kindly please share some feasibility details with this microprocessor and share block diagrams.

help me to create a VPX architecture with ADSP SC589 and guide to communicate VPX modules.

Using SHARC cores independently

JamesB — Tue, 05 Mar 2024 14:42:00 GMT

Hi all,

I'm using the SC-589 on some custom hardware, with the bare metal framework. The hardware is organised such that there are two ADCs (both the same device, same settings), and I would like to feed each on into its own SHARC core for processing. ADC1 and SHARC core 1 are working fine using elements of the bare metal framework with custom initialisation code for the ADC. There is not audio out for the application, so I'm calculating the RMS of each channel and feeding this out on the UART once per second. As per the bare metal framework, I'm using I2S data into SPORT0 on SHARC core 1.

For SHARC core 2, the code functionality requirement is identical, the only changes are that SPORT 4, connected via DAI1 is used instead of SPORT0 on DAI0.

The code for SHARC core 1 has been duplicated for core 2, with the exceptions of:

Changes to the SRU to connect the relevant DAI1 pins to SPORT4.
Use of DMA11 interrupt for SPORT4B data reception
Using a different TPU interrupt for the audio callback handler.

Whilst the code on SHARC core 1 works fine in terms of representative RMS values visible on the serial port, the values from the channels on SHARC core 2 are always 0. I've traced all the core 2 framework code through - both the dma handler and audio callback handler are working properly (checked with toggling pins on callback), and no samples are being dropped. Following the code back, and inserting known values into the buffers, it seems the issue is with the start of the dma routine - this seems to pull in only 0's to the input channels buffer:

    // Artificially fill buffers:
    for (i = 0; i < AUDIO_CHANNELS * AUDIO_BLOCK_SIZE; i++) {

        ADC2_audiochannels_in[i] = 1;
    }


    // This is where we're getting stuck - sport4_dma_rx_0_buffer or sport4_dma_rx_1_buffer seems to be pulling in 0's

    if (    (uint32_t)sport_dma_cfg->dma_descriptor_rx_0_list.Next_Desc !=
            (*sport_dma_cfg->pREG_DMA_RX_DSCPTR_NXT)
            )  {

        audioflow_float_to_fixed(ADC2_audiochannels_out, sport4_dma_tx_0_buffer, AUDIO_CHANNELS * AUDIO_BLOCK_SIZE);
        audioflow_fixed_to_float(sport4_dma_rx_0_buffer, ADC2_audiochannels_in,  AUDIO_CHANNELS * AUDIO_BLOCK_SIZE);



    }
    else
    {
        audioflow_float_to_fixed(ADC2_audiochannels_out, sport4_dma_tx_1_buffer, AUDIO_CHANNELS * AUDIO_BLOCK_SIZE);
        audioflow_fixed_to_float(sport4_dma_rx_1_buffer, ADC2_audiochannels_in,  AUDIO_CHANNELS * AUDIO_BLOCK_SIZE);


    }

Artificially filling the buffers with known values after this point results in the RMS value jumping as expected.

So it would seem that the issue would be to do with the SRU, however I've double checked this with the graphical Signal Routing Unit configuration, and using the code below:

    // Set up DAI pins as inputs and outputs for ADC 1
    SRU(LOW,  DAI0_PBEN16_I);        // ADC1 BCLK is an input
    SRU(LOW,  DAI0_PBEN17_I);        // ADC1 DAT is an input
    SRU(LOW,  DAI0_PBEN18_I);        // ADC1 WS Out is an input

    // Route BCLK and FS to SPORT 0 (which connects to DAI0)
    SRU(DAI0_PB16_O, SPT0_ACLK_I);     // route ADC1 BCLK pin to SPORT0A clock input
    SRU(DAI0_PB16_O, SPT0_BCLK_I);     // route ADC1 BCLK pin to SPORT0B clock input
    SRU(DAI0_PB18_O, SPT0_AFS_I);         // route ADC1 FS pin to SPORT0A frame sync
    SRU(DAI0_PB18_O, SPT0_BFS_I);         // route ADC1 FS pin to SPORT0B frame sync
    // Route data signals
    SRU(DAI0_PB17_O, SPT0_BD0_I);        // route ADC1 SDATA Out pin to SPORT0B-D0 input

//    SRU(HIGH,  DAI0_PBEN01_I);        // Loopback BCLK is an output
//    SRU(HIGH,  DAI0_PBEN02_I);        // Loopback DAT is an output
//    SRU(HIGH,  DAI0_PBEN03_I);        // Loopback WS Out is an output

//    Route out to exposed pads for debug
//    SRU(DAI0_PB16_O, DAI0_PB01_I);
//    SRU(DAI0_PB17_O, DAI0_PB02_I);
//    SRU(DAI0_PB18_O, DAI0_PB03_I);


    // Set up DAI pins as inputs and outputs for ADC 2
    SRU2(LOW,  DAI1_PBEN16_I);        // ADC2 BCLK is an input
    SRU2(LOW,  DAI1_PBEN17_I);        // ADC2 DAT is an input
    SRU2(LOW,  DAI1_PBEN18_I);        // ADC2 WS Out is an input



    // Route BCLK and FS to SPORT 4 (which connects to DAI1)
    SRU2(DAI1_PB16_O, SPT4_ACLK_I);     // route ADC2 BCLK pin to SPORT4A clock input
    SRU2(DAI1_PB16_O, SPT4_BCLK_I);     // route ADC2 BCLK pin to SPORT4B clock input
    SRU2(DAI1_PB18_O, SPT4_AFS_I);         // route ADC2 FS pin to SPORT4A frame sync
    SRU2(DAI1_PB18_O, SPT4_BFS_I);         // route ADC2 FS pin to SPORT4B frame sync
    // Route data signals
    SRU2(DAI1_PB17_O, SPT4_BD0_I);        // route ADC2 SDATA Out pin to SPORT4B-D0 input

//    SRU2(HIGH,  DAI1_PBEN01_I);        // Loopback BCLK is an output
//    SRU2(HIGH,  DAI1_PBEN02_I);        // Loopback DAT is an output
//    SRU2(HIGH,  DAI1_PBEN03_I);        // Loopback WS Out is an output

// 	  Route out to exposed pads for debug
//    SRU2(DAI1_PB16_O, DAI1_PB01_I);
//    SRU2(DAI1_PB17_O, DAI1_PB02_I);
//    SRU2(DAI1_PB18_O, DAI1_PB03_I);

Scoping test points show all the correct I2S signals are present on the right pins, and I can route the I2S data back out onto a spare test point on another DAI1 pin, which would seem to indicate the routing works, so I'm at a bit of a loss as to where the issue is. Any insight would be greatly appreciated!

SC589 SPI1 issues

JamesB — Fri, 16 Feb 2024 15:28:44 GMT

Hi All,

I've been using the Bare Metal Framework to develop code for the SC-589 both on custom hardware, and the ADZS-SC589-MINI development board.

Using the bm_spi driver, the SPI0 peripheral works fine, but SPI1 does not. A logic probe confirms normal function is observed for SPI0, however for SPI1, only chip select is actuated, but nothing happens on CLK and MOSI lines. The CLK and MOSI can be toggled manually, so I'm sure it's not a hardware issue, but I also cannot find and kind of peripheral clash for the pins in question that might prevent operation. Has anyone else had similar issues?

Example initialisation below,

		spi_initialize(&device->spi,
						   SPI_MODE_0,
						   SPI_SSEL_MANUAL,
						   SPI_WORDLEN_8BIT,
						   112500000,
						   SPI0);
spi_transfer(&device->spi, command);
// works correctly

		spi_initialize(&device->spi,
						   SPI_MODE_0,
						   SPI_SSEL_MANUAL,
						   SPI_WORDLEN_8BIT,
						   112500000,
						   SPI1);
spi_transfer(&device->spi, command);
// Does not

The correct CS, CLK and MOSI pins are monitored for each case, and CS is actuated manually within a transfer function.

Many thanks,

James

SHARC and partitionned convolution filter

TimeReverser — Mon, 12 Feb 2024 08:19:47 GMT

I'm performing partitioned convolution filtering using 12 ARM Cortex-M7 processors (IMXRT1062). The convolution code functions properly, but I'm encountering synchronization and memory issues.

Recently, I came across the SHARC family of processors, and they seem intriguing. Hence, I'm wondering if a single SHARC Audio Module could be powerful enough to replace all 12 of my Cortex-M7 processors?

Linux for ADSP‐SC5xx read audio from A2B bus

barbisanl — Thu, 25 Jan 2024 15:12:34 GMT

Hi Team,

I built the yocto image and uploaded successfully into the ADSP-SC589 following the guide: github.com/.../Getting-Started-with-ADSP‐SC589‐MINI-(Linux-for-ADSP‐SC5xx-Processors-3.1.0)
Then I also cross-compiled a simple server-client to send messages through the Ethernet to a PC.

Now I would like to read from the A2B bus the audio channels coming from the 4 microphones connected and send the raw data through the Ethernet.
Is there a guide to do this? Any suggestion about the library I should use to access the data on the A2B bus?

thanks