Hi all! I'm trying to adapt CCES Bare Metal Framework to work with external TDM source.
Board: SHARC Audio Module (ADSP-SC589)
TDM source spec:
- It generates SCLK
- SCLK frequency: 8.192
- 16 bit per sample
- 32 channels per frame
External source connected to the DAI1 pins:
- SCLK - DAI1_PIN11
- FS - DAI1_PIN02
- DIN (to source) - DAI1_PIN12
- DOUT (from source) - DAI1_PIN14
Also to this port connected logical analyser (for debug):
- DAI1_PIN03
- DAI1_PIN06
- DAI1_PIN13
- DAI1_PIN16
When I connect logic analyser to TDM source directly I can see correct signal:
My SRU configuration:
// Set up DAI pins as inputs and outputs SRU2(LOW, DAI1_PBEN11_I); // BCLK is an input SRU2(LOW, DAI1_PBEN02_I); // FS is an input SRU2(LOW, DAI1_PBEN14_I); // SDATA Out (from SPU) is an input SRU2(HIGH, DAI1_PBEN12_I); // SDATA In (to SPU) is an output // Route BCLK and FS to SPORT 4 (which connects to DAI1) SRU2(DAI1_PB11_O, SPT4_ACLK_I); // route BCLK pin to SPORT4A clock input SRU2(DAI1_PB11_O, SPT4_BCLK_I); // route BCLK pin to SPORT4B clock input SRU2(DAI1_PB02_O, SPT4_AFS_I); // route FS pin to SPORT4A frame sync SRU2(DAI1_PB02_O, SPT4_BFS_I); // route FS pin to SPORT4B frame sync // Route data signals SRU2(DAI1_PB14_O, SPT4_BD0_I); // route SDATA Out pin to SPORT4B-D0 input SRU2(SPT4_AD0_O, DAI1_PB12_I); // route SPORT4A-D0 output to SDATA In // Debug SRU2(HIGH, DAI1_PB03_I); SRU2(HIGH, DAI1_PB13_I); SRU2(HIGH, DAI1_PB16_I); SRU2(HIGH, DAI1_PB06_I); SRU2(DAI1_PB11_O, DAI1_PB03_I); SRU2(DAI1_PB02_O, DAI1_PB13_I); SRU2(DAI1_PB14_O, DAI1_PB16_I); SRU2(SPT4_AD0_O, DAI1_PB06_I);
My SPORT configuration:
SPORT_DMA_CONFIG SPR4_32CH_Config = {
.sport_number = SPORT4,
.dma_audio_channels = AUDIO_CHANNELS, // 32
.dma_audio_block_size = AUDIO_BLOCK_SIZE,
.dma_tx_buffer_0 = sport4_dma_tx_0_buffer,
.dma_tx_buffer_1 = sport4_dma_tx_1_buffer,
.dma_rx_buffer_0 = sport4_dma_rx_0_buffer,
.dma_rx_buffer_1 = sport4_dma_rx_1_buffer,
// SPORT Transmit
.pREG_SPORT_CTL_A = (0x1 << BITP_SPORT_CTL_A_DTYPE) | // Right justify, sign extend
(0xF << BITP_SPORT_CTL_A_SLEN) | // 16-bit transfers
BITM_SPORT_CTL_A_FSR | // Frame sync required
BITM_SPORT_CTL_A_LFS | // Active low FS / LR CLK
BITM_SPORT_CTL_A_SPTRAN | // SPORT is transmitter
0,
.pREG_SPORT_MCTL_A = BITM_SPORT_MCTL_A_MCE | // Multi-channel enable
(0x1 << BITP_SPORT_MCTL_A_MFD) | // Frame delay = 1
((AUDIO_CHANNELS - 1) << BITP_SPORT_MCTL_A_WSIZE) | // 32 words / frame
0,
.pREG_SPORT_CS0_A = AUDIO_CHANNELS_MASK, // 32 channels
// SPORT Receive
.pREG_SPORT_CTL_B = // (0x1 << BITP_SPORT_CTL_B_DTYPE) | // Right justify, sign extend
(0xF << BITP_SPORT_CTL_B_SLEN) | // 16-bit transfers
BITM_SPORT_CTL_B_FSR | // Frame sync required
BITM_SPORT_CTL_B_LFS | // Active low FS / LR CLK
0,
.pREG_SPORT_MCTL_B = BITM_SPORT_MCTL_B_MCE | // Multi-channel enable
(0x1 << BITP_SPORT_MCTL_B_MFD) | // Frame delay = 1
((AUDIO_CHANNELS - 1) << BITP_SPORT_MCTL_B_WSIZE) | // 32 words / frame
0,
.pREG_SPORT_CS0_B = AUDIO_CHANNELS_MASK, // 32 channels
.generates_interrupts = true,
.dma_interrupt_routine = audioframework_dma_handler
};
But I can't see any signals on debug pins and not receive DMA interrupt.
Any ideas?
PS Full dump of mmio registers:
