Category: Software
Product Number: ADSP-SC594
Hi, I have a customer board and need to enable more SPORTs in DTS and all run TDM8 format, so I have extended the sc594-som-ezkit.dts and sc59xx.dtsi
So far I can see that registration of the soundcards in Linux work well but when I start audio playback on any device except for the i2s4, I get errors.
Is there anything wrong with my configuration / DTS files or is there any issue that the SPORT drivers just support SPORT4 ?
# aplay -l
**** List of PLAYBACK Hardware Devices ****
card 0: sc5xxasoccard [sc5xx-asoc-card], device 0: TDM8 tdm8-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 1: sc5xxasoccard_1 [sc5xx-asoc-card], device 0: TDM8 tdm8-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 2: sc5xxasoccard_2 [sc5xx-asoc-card], device 0: TDM8 tdm8-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 3: sc5xxasoccard_3 [sc5xx-asoc-card], device 0: TDM8 tdm8-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 4: sc5xxasoccard_4 [sc5xx-asoc-card], device 0: TDM8 tdm8-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
aplay -Ddefault:CARD=sc5xxasoccard_3 -fS32_LE -t raw -c8 -r 48000 /mnt/tdm8_si
ne_silence.raw
Playing raw data '/mnt/tdm8_sine_silence.raw' : Signed 32 bit Little Endian, Rate 48000 Hz, Channels 8
adi-dma 31023000.dma: channel 4: dma with not-done status 0x76200
adi-dma 31023000.dma: channel 4: dma with not-done status 0x76200
adi-dma 31023000.dma: channel 4: dma with not-done status 0x76200
adi-dma 31023000.dma: channel 4: dma with not-done status 0x76200
adi-dma 31023000.dma: channel 4: dma with not-done status 0x76200
adi-dma 31023000.dma: channel 4: dma with not-done status 0x76200
adi-dma 31023000.dma: channel 4: dma with not-done status 0x76200
/*
* Device tree for ADI sc594-som-ezkit board
*
* Copyright 2014 - 2020 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/adi-adsp.h>
#include <dt-bindings/pinctrl/adi-adsp-sru.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "sc59x.dtsi"
/ {
model = "ADI sc594-som-ezkit";
compatible = "adi,sc594-som-ezkit", "adi,sc59x";
aliases {
};
memory@C3000000 {
device_type = "memory";
reg = <0xC3000000 0xF000000>;
};
#ifdef IGNORE_FOR_NOW
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
vdev0vrings: vdev0vring0@20010000 {
reg = <0x20010000 0x4000>;
no-map;
};
vdev0buffer: vdev0buffer@20014000 {
compatible = "shared-dma-pool";
reg = <0x20014000 0x20000>;
no-map;
};
vdev1vrings: vdev0vring0@20034000 {
reg = <0x20034000 0x4000>;
no-map;
};
vdev1buffer: vdev0buffer@20038000 {
compatible = "shared-dma-pool";
reg = <0x20038000 0x20000>;
no-map;
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsc_tbl0: rsc_tbl0@20000000 {
reg = <0x20000000 0x400>; /*1KiB*/
no-map;
};
rsc_tbl1: rsc_tbl0@20000400 {
reg = <0x20000400 0x400>; /*1KiB*/
no-map;
};
sram_B1_unused@20000800 {
reg = <0x20000800 0x4800>; /*18KiB*/
no-map;
};
sharc_internal_icc@20005000 {
reg = <0x20005000 0x20000>; /*128KiB*/
no-map;
};
};
#endif
scb {
sharc0: core1-rproc@0x28240000 {
compatible = "adi,remoteproc";
reg = <0x28240000 0x160000>,
<0x20000000 0x200000>;
core-id = <1>;
core-irq = <74>; /* SOFT1 */
firmware-name = "adi_adsp_core1_fw.ldr";
interrupts = <GIC_SPI 165 IRQ_TYPE_EDGE_RISING>; /* TRU0_SLV3 */
adi,rcu = <&rcu>;
adi,l1-da = <0x240000 0x3a0000>;
adi,l2-da = <0x20000000 0x20200000>;
/*adi,rsc-table = <&rsc_tbl0>;*/
adi,verify = <1>;
adi,tru = <&tru>;
adi,tru-master-id = <140>; /* trigger master SOFT4 */
status = "okay";
};
sharc1: core2-rproc@0x28a40000 {
compatible = "adi,remoteproc";
reg = <0x28a40000 0x160000>,
<0x20000000 0x200000>;
core-id = <2>;
core-irq = <75>; /* SOFT2 */
firmware-name = "adi_adsp_core2_fw.ldr";
interrupts = <GIC_SPI 165 IRQ_TYPE_EDGE_RISING>; /* TRU0_SLV3 */
adi,rcu = <&rcu>;
adi,l1-da = <0x240000 0x3a0000>;
adi,l2-da = <0x20000000 0x20200000>;
/*adi,rsc-table = <&rsc_tbl1>;*/
adi,verify = <1>;
adi,tru = <&tru>;
adi,tru-master-id = <141>; /* trigger master SOFT5 */
status = "okay";
};
a2b_slave_codec: a2b_slave_codec {
compatible = "sonavox,tdm8";
model = "tdm8";
status = "okay";
};
a2b_master_codec: a2b_master_codec {
compatible = "sonavox,tdm8";
model = "tdm8";
status = "okay";
};
adc_amp_codec: adc_amp_codec {
compatible = "sonavox,tdm8";
model = "tdm8";
status = "okay";
};
dsp_codec: dsp_codec {
compatible = "sonavox,tdm8";
model = "tdm8";
status = "okay";
};
amps_codec: amps_codec {
compatible = "sonavox,tdm8";
model = "tdm8";
status = "okay";
};
sound_a2b_slave {
compatible = "sc5xx,asoc-card";
adi,cpu-dai = <&i2s4>;
adi,codec = <&a2b_slave_codec>;
iram = <&sram1>;
};
sound_a2b_master {
compatible = "sc5xx,asoc-card";
adi,cpu-dai = <&i2s5>;
adi,codec = <&a2b_master_codec>;
iram = <&sram1>;
};
sound_adc_amp {
compatible = "sc5xx,asoc-card";
adi,cpu-dai = <&i2s0>;
adi,codec = <&adc_amp_codec>;
iram = <&sram1>;
};
sound_dsp {
compatible = "sc5xx,asoc-card";
adi,cpu-dai = <&i2s1>;
adi,codec = <&dsp_codec>;
iram = <&sram1>;
};
sound_amps {
compatible = "sc5xx,asoc-card";
adi,cpu-dai = <&i2s2>;
adi,codec = <&s_codec>;
iram = <&sram1>;
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_default>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_hwflow>;
status = "okay";
};
&rtc0 {
status = "disabled";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_default>;
status = "okay";
cs-gpios = <&gpa 9 GPIO_ACTIVE_LOW>,
<&gpa 10 GPIO_ACTIVE_LOW>;
spidev@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <5000000>;
reg = <0>;
};
spidev2@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <5000000>;
reg = <1>;
};
};
&spi2 {
pinctrl-names = "default";
pinctrl-0 = <&spi2_default>;
status = "okay";
cs-gpios = <&gpa 5 GPIO_ACTIVE_LOW>,
<&gpa 2 GPIO_ACTIVE_LOW>;
spidev@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <5000000>;
reg = <0>;
};
spidev@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <5000000>;
reg = <1>;
};
};
&spi3 {
pinctrl-names = "default";
pinctrl-0 = <&spi3_default>;
status = "okay";
cs-gpios = <&gpg 8 GPIO_ACTIVE_LOW>,
<&gpg 9 GPIO_ACTIVE_LOW>;
spidev@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <5000000>;
reg = <0>;
};
spidev@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <5000000>;
reg = <1>;
};
};
&ospi {
pinctrl-names = "default";
pinctrl-0 = <&ospi_default>;
status = "okay";
flash0: s28hl01gt@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "s28hl01gt";
reg = <0>;
/* Adjust as needed, depends on board signal integrity
-- I was seeing issues with data writes at faster speeds */
spi-max-frequency = <36000000>;
/*m25p,fast-read;*/
cdns,page-size = <256>;
cdns,block-size = <1024>;
cdns,read-delay = <4>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
cdns,tslch-ns = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x80000>;
};
partition@1 {
label = "U-Boot Environment 1";
reg = <0x80000 0x40000>;
};
partition@2 {
label = "U-Boot Environment 2";
reg = <0xC0000 0x40000>;
};
partition@3 {
label = "Device Tree Blob 1";
reg = <0x100000 0x40000>;
};
partition@4 {
label = "Device Tree Blob 2";
reg = <0x140000 0x40000>;
};
partition@5 {
label = "Kernel zImage 1";
reg = <0x200000 0x600000>;
};
partition@6 {
label = "Kernel zImage 2";
reg = <0x800000 0x600000>;
};
partition@7 {
label = "User Data";
reg = <0xE00000 0x0300000>;
};
partition@8 {
label = "Rootfs 1";
reg = <0x1100000 0x1800000>;
};
partition@9 {
label = "Rootfs 2";
reg = <0x2900000 0x1700000>;
};
};
};
};
&i2c0 {
status = "disabled";
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
};
&i2c4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
};
&i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
};
&i2s0 {
status = "okay";
};
&i2s1 {
status = "okay";
};
&i2s2 {
status = "okay";
};
&i2s4 {
pinctrl-names = "default";
pinctrl-0 = <&sru_dai1>;
status = "okay";
};
&i2s5 {
status = "okay";
};
&crc0 {
status = "disabled";
};
&crc1 {
status = "disabled";
};
&can0 {
pinctrl-names = "default";
/*pinctrl-0 = <&can0_default>;*/
phy-name = "tja1055";
phy-gpios = <&gpb 8 0>, /* en PB8 */
<&gpb 2 0x1>; /* stb PB2, GPIO_ACTIVE_LOW */
status = "disabled";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&can1_default>;
phy-name = "tja1145";
phy-spibus = /bits/ 16 <0>;
phy-spiclk = <1000000>;
phy-spics = /bits/ 16 <44>; /* GPIO_PC12 */
status = "disabled";
};
&emac0 {
snps,reset-active-low;
snps,reset-delays-us = <0 200 500>;
phy-handle = <&dp83867>;
phy-mode = "rmii-id";
pinctrl-names = "default";
pinctrl-0 = <ð0_default>;
status = "okay";
snps,mtl-rx-config = <&emac0rxconfig>;
snps,mtl-tx-config = <&emac0txconfig>;
emac0txconfig: tx-config {
snps,tx-queues-to-use = <3>;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,dcb-algorithm;
};
};
emac0rxconfig: rx-config {
snps,rx-queues-to-use = <1>;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,dcb-algorithm;
};
};
mdio0 {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
dp83867: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
};
};
};
&emac1 {
phy-handle = <&dp83848>;
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <ð1_default>;
status = "disabled";
mdio1 {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
dp83848: ethernet-phy@1 {
reg = <1>;
};
};
};
&usb0_phy {
reset-gpios = <&gpf 15 GPIO_ACTIVE_LOW>;
status = "okay";
};
&usb0 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&usbc0_default>;
status = "okay";
};
&icc0 {
adi,tru = <&tru>;
status = "okay";
};
/*
&mmc0 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_8bgrp>;
supports-highspeed;
status = "disabled";
};
&video_decoder {
pinctrl-names = "8bit", "16bit", "24bit";
pinctrl-0 = <&ppi0_8b>;
pinctrl-1 = <&ppi0_16b>;
pinctrl-2 = <&ppi0_24b>;
status = "disabled";
};
&video_encoder {
pinctrl-names = "8bit", "16bit", "24bit";
pinctrl-0 = <&ppi0_8b>;
pinctrl-1 = <&ppi0_16b>;
pinctrl-2 = <&ppi0_24b>;
status = "disabled";
};
*/
/*
&lp0 {
pinctrl-names = "default";
pinctrl-0 = <&lp0_default>;
status = "okay";
};
&lp1 {
pinctrl-names = "default";
pinctrl-0 = <&lp1_default>;
status = "okay";
};
*/
&sram_mmap {
status = "disabled";
};
&pinctrl0 {
uart0_default: uart0_default_pins {
pins {
pinmux = <ADI_ADSP_PINMUX('D', 8, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('D', 9, ADI_ADSP_PINFUNC_ALT0)>;
};
};
uart2_hwflow: uart2_hwflow_pins {
pins {
pinmux = <ADI_ADSP_PINMUX('D', 10, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('D', 11, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('D', 12, ADI_ADSP_PINFUNC_ALT1)>,
<ADI_ADSP_PINMUX('D', 13, ADI_ADSP_PINFUNC_ALT1)>;
};
};
spi0_default: spi0_default_pins {
pins {
pinmux = <ADI_ADSP_PINMUX('A', 6, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('A', 7, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('A', 8, ADI_ADSP_PINFUNC_ALT0)>;
};
};
spi2_default: spi2_default_pins {
pins {
pinmux = <ADI_ADSP_PINMUX('A', 0, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('A', 1, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('A', 4, ADI_ADSP_PINFUNC_ALT0)>;
};
};
spi3_default: spi3_default_pins {
pins {
pinmux = <ADI_ADSP_PINMUX('G', 5, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('G', 6, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('G', 7, ADI_ADSP_PINFUNC_ALT0)>;
};
};
ospi_default: ospi_default_pins {
pins {
pinmux = <ADI_ADSP_PINMUX('C', 8, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('C', 9, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('C', 10, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('C', 11, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('C', 12, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('C', 13, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('C', 14, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('C', 15, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('D', 0, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('D', 1, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('D', 4, ADI_ADSP_PINFUNC_ALT2)>;
};
};
i2c1_pins: i2c1_default_pins {
pins {
pinmux = <ADI_ADSP_PINMUX('B', 0, ADI_ADSP_PINFUNC_ALT1)>,
<ADI_ADSP_PINMUX('B', 1, ADI_ADSP_PINFUNC_ALT1)>;
};
};
i2c2_pins: i2c2_default_pins {
pins {
pinmux = <ADI_ADSP_PINMUX('A', 14, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('A', 15, ADI_ADSP_PINFUNC_ALT0)>;
};
};
i2c4_pins: i2c4_default_pins {
pins {
pinmux = <ADI_ADSP_PINMUX('C', 0, ADI_ADSP_PINFUNC_ALT1)>,
<ADI_ADSP_PINMUX('C', 1, ADI_ADSP_PINFUNC_ALT1)>;
};
};
i2c5_pins: i2c5_default_pins {
pins {
pinmux = <ADI_ADSP_PINMUX('C', 2, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('C', 3, ADI_ADSP_PINFUNC_ALT0)>;
};
};
eth0_default: eth0_default_pins {
pins {
pinmux = <ADI_ADSP_PINMUX('H', 3, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('H', 4, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('H', 5, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('H', 6, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('H', 7, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('H', 8, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('H', 9, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('H', 10, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('H', 11, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('H', 13, ADI_ADSP_PINFUNC_ALT0)>;
};
};
eth1_default: eth1_default_pins {
pins {
pinmux = <ADI_ADSP_PINMUX('E', 11, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('E', 12, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('E', 13, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('E', 14, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('E', 15, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('F', 0, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('F', 1, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('F', 2, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('F', 3, ADI_ADSP_PINFUNC_ALT0)>;
};
};
mmc0_8bgrp: mmc0_8bgrp_pins {
pins {
pinmux = <ADI_ADSP_PINMUX('F', 2, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('F', 3, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('F', 4, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('F', 5, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('F', 6, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('F', 7, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('F', 8, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('F', 9, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('F', 10, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('F', 11, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('F', 12, ADI_ADSP_PINFUNC_ALT0)>;
};
};
usbc0_default: usbc0_default_pins {
pins {
pinmux = <ADI_ADSP_PINMUX('F', 3, ADI_ADSP_PINFUNC_ALT2)>,
<ADI_ADSP_PINMUX('F', 4, ADI_ADSP_PINFUNC_ALT2)>,
<ADI_ADSP_PINMUX('F', 5, ADI_ADSP_PINFUNC_ALT2)>,
<ADI_ADSP_PINMUX('F', 6, ADI_ADSP_PINFUNC_ALT2)>,
<ADI_ADSP_PINMUX('F', 7, ADI_ADSP_PINFUNC_ALT2)>,
<ADI_ADSP_PINMUX('F', 8, ADI_ADSP_PINFUNC_ALT2)>,
<ADI_ADSP_PINMUX('F', 9, ADI_ADSP_PINFUNC_ALT2)>,
<ADI_ADSP_PINMUX('F', 10, ADI_ADSP_PINFUNC_ALT2)>,
<ADI_ADSP_PINMUX('F', 11, ADI_ADSP_PINFUNC_ALT2)>,
<ADI_ADSP_PINMUX('F', 12, ADI_ADSP_PINFUNC_ALT2)>,
<ADI_ADSP_PINMUX('F', 13, ADI_ADSP_PINFUNC_ALT2)>,
<ADI_ADSP_PINMUX('F', 14, ADI_ADSP_PINFUNC_ALT2)>;
};
};
can1_default: can1_default_pins {
pins {
pinmux = <ADI_ADSP_PINMUX('G', 1, ADI_ADSP_PINFUNC_ALT0)>,
<ADI_ADSP_PINMUX('G', 2, ADI_ADSP_PINFUNC_ALT0)>;
};
};
};
&sru_ctrl_dai0 {
status = "okay";
sru_dai0: sru_dai0_mux {
route {
sru-routing =
<DAI0_HIGH_F DAI0_PBEN01_I>, /* set DAI0_PIN01 to output */
<SPT0_AD0_O_BD DAI0_PB01_I>, /* route DAI0_PIN01 to SPT0_AD0 */
<DAI0_LOW_F DAI0_PBEN02_I>, /* set DAI0_PIN02 to input */
<DAI0_PB01_O_ABCDE SPT0_BD0_I>, /* route DAI1_PIN02 to SPT0_BD0 */
<DAI0_HIGH_F DAI0_PBEN03_I>, /* set DAI1_PIN03 to output */
<SPT0_ACLK_O_A DAI0_PB03_I>, /* route SPT0_ACLK to DAI1_PIN03 */
<SPT0_ACLK_O_A SPT0_BCLK_I>, /* route SPT0_ACLK to SPT0_BLCK */
<DAI0_HIGH_F DAI0_PBEN04_I>, /* set DAI1_PIN04 to output */
<SPT0_AFS_O_D DAI0_PB04_I>, /* route SPT0_AFS to DAI1_PIN04 */
<SPT0_AFS_O_D SPT0_BFS_I>, /* route SPT0_AFS to SPT0_BFS */
<DAI0_LOW_F DAI0_PBEN05_I>, /* set DAI0_PIN05 to intput */
<DAI0_PB05_O_ABCDE SPT1_BD0_I>, /* route DAI0_PIN5 to SPT1_BD0 */
<DAI0_HIGH_F DAI0_PBEN06_I>, /* set DAI0_PIN06 to output */
<SPT1_AD0_O_BD DAI0_PB06_I>, /* route SPT1_AD0 to DAI0_PIN6 */
<DAI0_HIGH_F DAI0_PBEN07_I>, /* set DAI1_PIN07 to output */
<SPT1_ACLK_O_A DAI0_PB07_I>, /* route SPT1_ACLK to DAI1_PIN07 */
<SPT1_ACLK_O_A SPT1_BCLK_I>, /* route SPT1_ACLK to SPT1_BLCK */
<DAI0_HIGH_F DAI0_PBEN08_I>, /* set DAI1_PIN08 to output */
<SPT1_AFS_O_D DAI0_PB04_I>, /* route SPT1_AFS to DAI1_PIN08 */
<SPT1_AFS_O_D SPT1_BFS_I>, /* route SPT1_AFS to SPT1_BFS */
<DAI0_HIGH_F DAI0_PBEN09_I>, /* set DAI0_PIN09 to output */
<SPT2_AD0_O_BD DAI0_PB09_I>, /* route SPT2_AD0 to DAI0_PIN09 */
<DAI0_HIGH_F DAI0_PBEN10_I>, /* set DAI0_PIN10 to input */
<SPT2_AD1_O_BD DAI0_PB10_I>, /* route SPT2_AD1 to DAI0_PIN10 */
<DAI0_HIGH_F DAI0_PBEN11_I>, /* set DAI0_PIN11 to output */
<SPT2_BD0_O_BD DAI0_PB11_I>, /* route SPT2_BD0 to DAI0_PIN11 */
<DAI0_HIGH_F DAI0_PBEN12_I>, /* set DAI0_PIN12 to input */
<SPT2_BD1_O_BD DAI0_PB12_I>, /* route SPT2_BD1 to DAI0_PIN12 */
<DAI0_HIGH_F DAI0_PBEN19_I>, /* set DAI0_PIN19 to output */
<SPT2_ACLK_O_A DAI0_PB19_I>, /* route SPT2_ACLK to DAI0_PIN19 */
<SPT2_ACLK_O_A SPT2_BCLK_I>, /* route SPT2_ACLK to SPT2_BLCK */
<DAI0_HIGH_F DAI0_PBEN20_I>, /* set DAI0_PIN20 to output */
<SPT2_AFS_O_D DAI0_PB20_I>, /* route SPT2_AFS to DAI0_PIN20 */
<SPT2_AFS_O_D SPT2_BFS_I>; /* route SPT2_AFS to SPT2_BFS */
};
};
};
&sru_ctrl_dai1 {
status = "okay";
sru_dai1: sru_dai1_mux {
route {
sru-routing =
<DAI1_LOW_F DAI1_PBEN01_I>, /* set DAI1_PIN0B to input */
<DAI1_PB01_O_ABCDE SPT4_BD0_I>, /* route DAI1_PIN0B to SPT4_BD0 */
<DAI1_HIGH_F DAI1_PBEN02_I>, /* set DAI1_PIN02 to output */
<SPT4_AD0_O_BD DAI1_PB02_I>, /* route SPT4_AD0 to DAI1_PIN02 */
<DAI1_LOW_F DAI1_PBEN03_I>, /* set DAI1_PIN03 to input */
<DAI1_PB03_O_ABCDE SPT4_ACLK_I>, /* route DAI1_PIN03 to SPT4_ACLK */
<DAI1_PB03_O_ABCDE SPT4_BCLK_I>, /* route DAI1_PIN03 to SPT4_BCLK */
<DAI1_LOW_F DAI1_PBEN04_I>, /* set DAI1_PIN4 to input */
<DAI1_PB04_O_ABCDE SPT4_AFS_I>, /* route DAI1_PIN4 to SPT4_AFS */
<DAI1_PB04_O_ABCDE SPT4_BFS_I>, /* route DAI1_PIN4 to SPT4_BFS */
<DAI1_LOW_F DAI1_PBEN05_I>, /* set DAI1_PIN5B to input */
<DAI1_PB05_O_ABCDE SPT5_BD0_I>, /* route DAI1_PIN5B to SPT5_BD0 */
<DAI1_HIGH_F DAI1_PBEN06_I>, /* set DAI1_PIN06 to output */
<SPT5_AD0_O_BD DAI1_PB06_I>, /* route SPT5_AD0 to DAI1_PIN06 */
<DAI1_HIGH_F DAI1_PBEN07_I>, /* set DAI1_PIN07 to output */
<SPT5_ACLK_O_D DAI1_PB07_I>, /* route DAI1_PIN07 to SPT5_ACLK */
<SPT5_ACLK_O_A SPT5_BCLK_I>, /* route DAI1_PIN07 to SPT5_BCLK */
<DAI1_HIGH_F DAI1_PBEN08_I>, /* set DAI1_PIN8 to output */
<SPT5_AFS_O_D DAI1_PB08_I>, /* route DAI1_PIN8 to SPT5_AFS */
<SPT5_AFS_O_C SPT5_BFS_I>; /* route SPT5_AFS to SPT5_BFS */
};
};
};
&tru {
rpmsg_to_a55: channel@0 {
adi,tru-master-id = <139>; /* trigger master SOFT3 */
adi,tru-slave-id = <160>; /* TRU0_IRQ3 */
};
rpmsg_to_sharc0: channel@1 {
adi,tru-master-id = <140>; /* trigger master SOFT4 */
adi,tru-slave-id = <164>; /* TRU0_IRQ7 */
};
rpmsg_to_sharc1: channel@2 {
adi,tru-master-id = <141>; /* trigger master SOFT5 */
adi,tru-slave-id = <168>; /* TRU0_IRQ11 */
};
};
/*
* Device tree header for ADI sc59x processor
*
* Copyright 2014 - 2018 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*
*/
#include <dt-bindings/input/adi_gp_counter.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/adi-sc5xx-clock.h>
/ {
model = "ADI sc59x";
compatible = "adi,sc59x";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases {
serial0 = &uart0;
serial2 = &uart2;
timer0 = &gptimer0;
timer1 = &gptimer1;
timer2 = &gptimer2;
timer3 = &gptimer3;
timer4 = &gptimer4;
timer5 = &gptimer5;
timer6 = &gptimer6;
timer7 = &gptimer7;
ethernet0 = &emac0;
ethernet1 = &emac1;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
spi3 = &spi3;
can0 = &can0;
can1 = &can1;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c4 = &i2c4;
i2c5 = &i2c5;
rtc0 = &rtc0;
i2s0 = &i2s0;
i2s1 = &i2s1;
i2s2 = &i2s2;
i2s3 = &i2s3;
i2s4 = &i2s4;
mmc0 = &mmc0;
sru0 = &sru_ctrl_dai0;
sru1 = &sru_ctrl_dai1;
};
cpus {
#size-cells = <0>;
#address-cells = <1>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a5";
reg = <0x0>;
clocks = <&clk ADSP_SC594_CLK_ARM>;
};
};
pmu {
compatible = "arm,cortex-a5-pmu";
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@310B2000 {
compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x310B2000 0x1000>,
<0x310B4000 0x100>;
};
L2: cache-controller@10000000 {
compatible = "arm,pl310-cache";
reg = <0x10000000 0x1000>;
cache-level = <2>;
};
sram0: sram-icc@20000000 { /* ICC SRAM 8KB */
compatible = "mmio-sram";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x20000000 0x2000>;
ranges = <0 0x20000000 0x2000>;
/* 1KB - Shared between SHARC cores*/
reserved@0{
reg = <0x0 0x400>;
label = "SHARC_common";
};
/* 1KB - Reserved resource_tables for SHARC cores*/
resource_table@1000{
reg = <0x1000 0x400>;
label = "SHARC_resource_tables";
};
};
sram1: sram-reserved@20100000 {
compatible = "mmio-sram";
reg = <0x20100000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x20100000 0x100000>;
};
sys_clkin0: sys-clkin0@1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "sys_clkin0";
};
sys_clkin1: sys-clkin1@2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "sys_clkin1";
};
clk: clocks@0x3108d000 {
compatible = "adi,sc594-clocks";
reg = <0x3108d000 0x1000>,
<0x3108e000 0x1000>,
<0x3108f000 0x1000>;
#clock-cells = <1>;
clocks = <&sys_clkin0>, <&sys_clkin1>;
clock-names = "sys_clkin0", "sys_clkin1";
status = "okay";
};
gptimers: gptimers@0x31018000 {
compatible = "adi,sc5xx-gptimers";
reg = <0x31018000 0x200>;
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
gptimer0: gptimer@0 {
reg = <0>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
adi,offset = <0x60>;
adi,is-clocksource;
adi,reset-timer;
};
gptimer1: gptimer@1 {
reg = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
adi,offset = <0x80>;
adi,is-clockevent;
adi,reset-timer;
};
gptimer2: gptimer@2 {
reg = <2>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
adi,offset = <0xa0>;
};
gptimer3: gptimer@3 {
reg = <3>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
adi,offset = <0xc0>;
};
gptimer4: gptimer@4 {
reg = <4>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
adi,offset = <0xe0>;
};
gptimer5: gptimer@5 {
reg = <5>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
adi,offset = <0x100>;
};
gptimer6: gptimer@6 {
reg = <6>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
adi,offset = <0x120>;
};
gptimer7: gptimer@7 {
reg = <7>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
adi,offset = <0x140>;
};
};
scb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
pads_system_config: adi-control@31004600 {
compatible = "adi,pads-system-config";
reg = <0x31004600 0x100>;
status = "okay";
};
sram-controller@31080000 {
compatible = "adi,sram-controller";
reg = <0x31080000 0x100>;
adi,sram = <&sram0>, <&sram1>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
sram_mmap: sram-mmap@0 { /* mmap from sram1 pool*/
compatible = "adi,sram-mmap";
adi,sram = <&sram1>;
status = "disabled";
};
rcu: rcu@0x3108C000 {
compatible = "adi,reset-controller";
reg = <0x3108C000 0x1000>;
adi,sharc-min = <1>;
adi,sharc-max = <2>;
status = "okay";
};
sec: sec@0x31089000 {
compatible = "adi,system-event-controller";
reg = <0x31089000 0x1000>;
adi,rcu = <&rcu>;
adi,sharc-cores = <2>;
status = "okay";
};
tru: tru@0x3108A000 {
compatible = "adi,trigger-routing-unit";
reg = <0x3108A000 0x1000>;
adi,max-master-id = <177>;
adi,max-slave-id = <188>;
status = "okay";
};
rtc0: rtc@0x310C8000 {
compatible = "adi,rtc2";
reg = <0x310C8000 0x100>;
/*interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;*/
calibration = /bits/ 8 <0>;
status = "disabled";
};
uart0: uart@0x31003000 {
compatible = "adi,uart4";
reg = <0x31003000 0x40>;
dmas = <&dma_cluster2 20>, <&dma_cluster2 21>;
dma-names = "tx", "rx";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk0";
status = "disabled";
};
uart1: uart@0x31003400 {
compatible = "adi,uart4";
reg = <0x31003400 0x40>;
dmas = <&dma_cluster2 34>, <&dma_cluster2 35>;
dma-names = "tx", "rx";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk0";
status = "disabled";
};
uart2: uart@0x31003800 {
compatible = "adi,uart4";
reg = <0x31003800 0x40>;
dmas = <&dma_cluster2 37>, <&dma_cluster2 38>;
dma-names = "tx", "rx";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk0";
status = "disabled";
};
can0: can@0x31000200 {
compatible = "adi,can";
reg = <0x31000200 0x5FF>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
can1: can@0x31000a00 {
compatible = "adi,can";
reg = <0x31000a00 0x5FF>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c0: twi@0x31001400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,twi";
reg = <0x31001400 0xFF>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
clock-khz = <100>;
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk0";
status = "disabled";
};
i2c1: twi@0x31001500 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,twi";
reg = <0x31001500 0xFF>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
clock-khz = <100>;
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk0";
status = "disabled";
};
i2c2: twi@0x31001600 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,twi";
reg = <0x31001600 0xFF>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clock-khz = <100>;
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk0";
status = "disabled";
};
i2c4: twi@0x31001100 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,twi";
reg = <0x31001100 0xFF>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clock-khz = <100>;
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk0";
status = "disabled";
};
i2c5: twi@0x31001200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,twi";
reg = <0x31001200 0xFF>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clock-khz = <100>;
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk0";
status = "disabled";
};
i2s0: i2s@0 {
compatible = "sc5xx,i2s-dai";
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk";
status = "disabled";
reg = <0x31002000 0x80>, <0x31002080 0x80>;
sport-channel = <0>;
interrupt-names = "tx_status", "rx_status";
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sport_dma_cluster 0>, <&sport_dma_cluster 1>;
dma-names = "tx", "rx";
iram = <&sram1>;
};
i2s1: i2s@1 {
compatible = "sc5xx,i2s-dai";
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk";
status = "disabled";
reg = <0x31002100 0x80>, <0x31002180 0x80>;
sport-channel = <1>;
interrupt-names = "tx_status", "rx_status";
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sport_dma_cluster 2>, <&sport_dma_cluster 3>;
dma-names = "tx", "rx";
iram = <&sram1>;
};
i2s2: i2s@2 {
compatible = "sc5xx,i2s-dai";
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk";
status = "disabled";
reg = <0x31002200 0x80>, <0x31002280 0x80>;
sport-channel = <2>;
interrupt-names = "tx_status", "rx_status";
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sport_dma_cluster 4>, <&sport_dma_cluster 5>;
dma-names = "tx", "rx";
iram = <&sram1>;
};
i2s3: i2s@3 {
compatible = "sc5xx,i2s-dai";
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk";
status = "disabled";
reg = <0x31002300 0x80>, <0x31002380 0x80>;
sport-channel = <3>;
interrupt-names = "tx_status", "rx_status";
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sport_dma_cluster 6>, <&sport_dma_cluster 7>;
dma-names = "tx", "rx";
iram = <&sram1>;
};
i2s4: i2s@4 {
compatible = "sc5xx,i2s-dai";
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk";
status = "disabled";
reg = <0x31002400 0x80>, <0x31002480 0x80>;
sport-channel = <4>;
interrupt-names = "tx_status", "rx_status";
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sport_dma_cluster 10>, <&sport_dma_cluster 11>;
dma-names = "tx", "rx";
iram = <&sram1>;
};
i2s5: i2s@5 {
compatible = "sc5xx,i2s-dai";
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "sclk";
status = "disabled";
reg = <0x31002500 0x80>, <0x31002580 0x80>;
sport-channel = <5>;
interrupt-names = "tx_status", "rx_status";
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sport_dma_cluster 12>, <&sport_dma_cluster 13>;
dma-names = "tx", "rx";
iram = <&sram1>;
};
watchdog@0x31008000 {
compatible = "arm,adi-watchdog";
reg = <0x31008000 0x10>;
timeout-sec = <30>;
clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>;
clock-names = "adi-watchdog";
};
spi0: spi@0x3102e000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,spi3";
reg = <0x3102e000 0xFF>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
dma-channel = <22>, <23>;
clocks = <&clk ADSP_SC594_CLK_SPI>;
clock-names = "spi";
status = "disabled";
};
spi1: spi@0x3102f000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,spi3";
reg = <0x3102f000 0xFF>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
dma-channel = <24>, <25>;
dmas = <&spi_cluster 24>, <&spi_cluster 25>;
clocks = <&clk ADSP_SC594_CLK_SPI>;
clock-names = "spi";
status = "disabled";
};
spi2: spi@0x31030000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,spi3";
reg = <0x31030000 0xFF>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&spi_cluster 26>, <&spi_cluster 27>;
dma-names = "tx", "rx";
clocks = <&clk ADSP_SC594_CLK_SPI>;
clock-names = "spi";
status = "disabled";
};
spi3: spi@0x31031000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,spi3";
reg = <0x31031000 0xFF>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&spi_cluster 55>, <&spi_cluster 56>;
dma-names = "tx", "rx";
clocks = <&clk ADSP_SC594_CLK_SPI>;
clock-names = "spi";
status = "disabled";
};
ospi: spi@31027000 {
compatible = "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x31027000 0x1000>,
<0x60000000 0x10000000>;
interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk ADSP_SC594_CLK_OSPI>;
clock-names = "ospi";
cdns,is-decoded-cs;
cdns,fifo-depth = <128>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x00000000>;
status = "disabled";
};
emac0: ethernet@0x31040000 {
compatible = "adi,dwmac", "snps,dwmac-3.710", "snps,dwmac";
reg = <0x31040000 0x2000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
snps,mixed-burst;
snps,pbl = <8>;
snps,force_sf_dma_mode;
snps,perfect-filter-entries = <32>;
clocks = <&clk ADSP_SC594_CLK_GIGE>;
clock-names = "stmmaceth";
adi,system-config = <&pads_system_config>;
status = "disabled";
};
emac1: ethernet@0x31042000 {
compatible = "adi,dwmac", "snps,dwmac-3.710", "snps,dwmac";
reg = <0x31042000 0x2000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
snps,fixed-burst;
snps,burst_len = <0x4>; /* BLEN8 */
snps,pbl = <1>;
snps,force_thresh_dma_mode;
clocks = <&clk ADSP_SC594_CLK_GIGE>;
clock-names = "stmmaceth";
status = "disabled";
};
icc0: icc@0 {
compatible = "adi,icc";
reg = <0x20000000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 165 IRQ_TYPE_EDGE_RISING>;
peerinfo = <1 140>, <2 141>;
status = "disabled";
};
core_ctrl0: core_ctrl@0 {
compatible = "adi,core_ctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x3108C000 0x80>; /* RCU0 control reg base */
adi,icc_mem = <&icc0>;
};
crc0: crc@0x31001200 {
compatible = "adi,hmac-crc";
reg = <0x31001200 0xFF>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
dma_channel = <8>;
crypto_crc_poly = <0x5c5c5c5c>;
status = "disabled";
};
crc1: crc@0x31001300 {
compatible = "adi,hmac-crc";
reg = <0x31001300 0xFF>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
dma_channel = <18>;
crypto_crc_poly = <0x5c5c5c5c>;
status = "disabled";
};
pinctrl0: pinctrl@0x31004600 {
compatible = "adi,adsp-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x31004600 0x400>;
adi,port-sizes = <16 16 16 16 16 16 16 16 7>;
};
sru_ctrl_dai0: sru-ctrl-dai0@0x310C9000 {
compatible = "adi,adsp-sru-ctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x310C9000 0x224>;
adi,system-config = <&pads_system_config>;
status = "disabled";
};
sru_ctrl_dai1: sru-ctrl-dai1@0x310CA000 {
compatible = "adi,adsp-sru-ctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x310CA000 0x224>;
adi,system-config = <&pads_system_config>;
status = "disabled";
};
mmc0: mmc@0x31010000 {
compatible = "adi,mmc";
reg = <0x31010000 0xFFF>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <58>;
#address-cells = <1>;
#size-cells = <0>;
fifo-depth = <1024>;
status = "disabled";
};
/*
video_decoder: cap@0x31040000 {
compatible = "adi,cap";
card-name = "SC58X";
type = <2>;
dma-channel = <28>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x31040000 0xfff>;
spu_securep_id = <95>;
i2c_bus_id = <0>;
status = "disabled";
};
*/
gp_counter: cnt@0x3100B000 {
compatible = "adi,gp_counter";
reg = <0x3100B000 0xFF>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
/*
video_encoder: disp@0x31040000 {
compatible = "adi,disp";
card-name = "SC58X";
type = <2>;
dma-channel = <28>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x31040000 0xfff>;
spu_securep_id = <95>;
i2c_bus_id = <0>;
status = "disabled";
};
*/
lp0: linkport@0 {
compatible = "linkport0";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
status = "disabled";
};
lp1: linkport@1 {
compatible = "linkport1";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clock-div = <1>;
status = "disabled";
};
pint0: pint@0x31005000 {
compatible = "adi,adsp-pint";
reg = <0x31005000 0xFF>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
};
pint1: pint@0x31005100 {
compatible = "adi,adsp-pint";
reg = <0x31005100 0xFF>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
};
pint2: pint@0x31005200 {
compatible = "adi,adsp-pint";
reg = <0x31005200 0xFF>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
};
pint3: pint@0x31005300 {
compatible = "adi,adsp-pint";
reg = <0x31005300 0xFF>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
};
pint4: pint@0x31005400 {
compatible = "adi,adsp-pint";
reg = <0x31005400 0xFF>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
};
pint5: pint@0x31005500 {
compatible = "adi,adsp-pint";
reg = <0x31005500 0xFF>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
};
pint6: pint@0x31005600 {
compatible = "adi,adsp-pint";
reg = <0x31005600 0xFF>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};
pint7: pint@0x31005700 {
compatible = "adi,adsp-pint";
reg = <0x31005700 0xFF>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
};
gpa: gport@0x31004000 {
compatible = "adi,adsp-port-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x31004000 0x7F>;
gpio-ranges = <&pinctrl0 0 0 16>;
adi,pint = <&pint0 1>;
adi,gpio-base = <0>;
};
gpb: gport@0x31004080 {
compatible = "adi,adsp-port-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x31004080 0x7F>;
gpio-ranges = <&pinctrl0 0 16 16>;
adi,pint = <&pint0 0>;
adi,gpio-base = <16>;
};
gpc: gport@0x31004100 {
compatible = "adi,adsp-port-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x31004100 0x7F>;
gpio-ranges = <&pinctrl0 0 32 16>;
adi,pint = <&pint2 1>;
adi,gpio-base = <32>;
};
gpd: gport@0x31004180 {
compatible = "adi,adsp-port-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x31004180 0x7F>;
gpio-ranges = <&pinctrl0 0 48 16>;
adi,pint = <&pint2 0>;
adi,gpio-base = <48>;
};
gpe: gport@0x31004200 {
compatible = "adi,adsp-port-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x31004200 0x7F>;
gpio-ranges = <&pinctrl0 0 64 16>;
adi,pint = <&pint4 1>;
adi,gpio-base = <64>;
};
gpf: gport@0x31004280 {
compatible = "adi,adsp-port-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x31004280 0x7F>;
gpio-ranges = <&pinctrl0 0 80 16>;
adi,pint = <&pint4 0>;
adi,gpio-base = <80>;
};
gpg: gport@0x31004300 {
compatible = "adi,adsp-port-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x31004300 0x7F>;
gpio-ranges = <&pinctrl0 0 96 16>;
adi,pint = <&pint6 1>;
adi,gpio-base = <96>;
};
gph: gport@0x31004380 {
compatible = "adi,adsp-port-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x31004380 0x7F>;
gpio-ranges = <&pinctrl0 0 112 16>;
adi,pint = <&pint6 0>;
adi,gpio-base = <112>;
};
gpi: gport@0x31004400 {
compatible = "adi,adsp-port-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x31004400 0x7F>;
gpio-ranges = <&pinctrl0 0 128 7>;
adi,pint = <&pint7 1>;
adi,gpio-base = <128>;
};
usb0_phy: usbphy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
status = "disabled";
};
usb0: usb@310c5000 {
compatible = "adi,adsp2159x-usbc", "snps,dwc2";
reg = <0x310c5000 0x4000>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb0_phy>;
phy-names = "usb2-phy";
status = "disabled";
};
/*
dma0: dma@0 {
compatible = "adi,dma2";
reg = <0x31022000 0x7F>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <66>;
};
dma1: dma@1 {
compatible = "adi,dma2";
reg = <0x31022080 0x7F>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <67>;
};
dma2: dma@2 {
compatible = "adi,dma2";
reg = <0x31022100 0x7F>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <68>;
};
dma3: dma@3 {
compatible = "adi,dma2";
reg = <0x31022180 0x7F>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <69>;
};
dma4: dma@4 {
compatible = "adi,dma2";
reg = <0x31022200 0x7F>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <70>;
};
dma5: dma@5 {
compatible = "adi,dma2";
reg = <0x31022280 0x7F>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <71>;
};
dma6: dma@6 {
compatible = "adi,dma2";
reg = <0x31022300 0x7F>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <72>;
};
dma7: dma@7 {
compatible = "adi,dma2";
reg = <0x31022380 0x7F>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <73>;
};
dma8: dma@8 {
compatible = "adi,dma2";
reg = <0x310A7000 0x7F>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <74>;
};
dma9: dma@9 {
compatible = "adi,dma2";
reg = <0x310A7080 0x7F>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <75>;
};
dma10: dma@10 {
compatible = "adi,dma2";
reg = <0x31023000 0x7F>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <76>;
};
dma11: dma@11 {
compatible = "adi,dma2";
reg = <0x31023080 0x7F>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <77>;
};
dma12: dma@012 {
compatible = "adi,dma2";
reg = <0x31023100 0x7F>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <78>;
};
dma13: dma@13 {
compatible = "adi,dma2";
reg = <0x31023180 0x7F>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <79>;
};
dma14: dma@14 {
compatible = "adi,dma2";
reg = <0x31023200 0x7F>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <80>;
};
dma15: dma@15 {
compatible = "adi,dma2";
reg = <0x31023280 0x7F>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <81>;
};
dma16: dma@16 {
compatible = "adi,dma2";
reg = <0x31023300 0x7F>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <82>;
};
dma17: dma@17 {
compatible = "adi,dma2";
reg = <0x31023380 0x7F>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <83>;
};
dma18: dma@18 {
compatible = "adi,dma2";
reg = <0x310A7100 0x7F>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <84>;
};
dma19: dma@19 {
compatible = "adi,dma2";
reg = <0x310A7180 0x7F>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <85>;
};
dma20: dma@20 {
compatible = "adi,dma2";
reg = <0x31026080 0x7F>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <86>;
};
dma21: dma@21 {
compatible = "adi,dma2";
reg = <0x31026000 0x7F>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <87>;
};
dma22: dma@22 {
compatible = "adi,dma2";
reg = <0x3102D000 0x7F>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <88>;
};
dma23: dma@23 {
compatible = "adi,dma2";
reg = <0x3102D080 0x7F>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <89>;
};
dma24: dma@24 {
compatible = "adi,dma2";
reg = <0x3102D100 0x7F>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <90>;
};
dma25: dma@25 {
compatible = "adi,dma2";
reg = <0x3102D180 0x7F>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <91>;
};
dma26: dma@26 {
compatible = "adi,dma2";
reg = <0x3102D200 0x7F>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <92>;
};
dma27: dma@27 {
compatible = "adi,dma2";
reg = <0x3102D280 0x7F>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <93>;
};
dma28: dma@28 {
compatible = "adi,dma2";
reg = <0x31026400 0x7F>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <94>;
};
dma29: dma@29 {
compatible = "adi,dma2";
reg = <0x31026480 0x7F>;
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <95>;
};
dma30: dma@30 {
compatible = "adi,dma2";
reg = <0x30FFF000 0x7F>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <96>;
};
dma34: dma@34 {
compatible = "adi,dma2";
reg = <0x31026180 0x7F>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <97>;
};
dma35: dma@35 {
compatible = "adi,dma2";
reg = <0x31026100 0x7F>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <98>;
};
dma36: dma@36 {
compatible = "adi,dma2";
reg = <0x30FFF080 0x7F>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <99>;
};
dma37: dma@37 {
compatible = "adi,dma2";
reg = <0x31026280 0x7F>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <100>;
};
dma38: dma@38 {
compatible = "adi,dma2";
reg = <0x31026200 0x7F>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <101>;
};
dma39: dma@39 {
compatible = "adi,dma2";
reg = <0x3109A000 0x7F>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <102>;
};
dma40: dma@40 {
compatible = "adi,dma2";
reg = <0x3109A080 0x7F>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <103>;
};
dma43: dma@43 {
compatible = "adi,dma2";
reg = <0x3109B000 0x7F>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <104>;
};
dma44: dma@44 {
compatible = "adi,dma2";
reg = <0x3109B080 0x7F>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <105>;
};
dma45: dma@45 {
compatible = "adi,dma2";
reg = <0x310A7200 0x7F>;
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <106>;
};
dma46: dma@46 {
compatible = "adi,dma2";
reg = <0x310A7280 0x7F>;
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <106>;
};
dma47: dma@47 {
compatible = "adi,dma2";
reg = <0x310A7300 0x7F>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <106>;
};
dma48: dma@48 {
compatible = "adi,dma2";
reg = <0x310A7380 0x7F>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <106>;
};
dma49: dma@49 {
compatible = "adi,dma2";
reg = <0x310AC000 0x7F>;
interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <106>;
};
dma50: dma@50 {
compatible = "adi,dma2";
reg = <0x310AC080 0x7F>;
interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <106>;
};
dma51: dma@51 {
compatible = "adi,dma2";
reg = <0x3109C000 0x7F>;
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <106>;
};
dma52: dma@52 {
compatible = "adi,dma2";
reg = <0x3109C080 0x7F>;
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <106>;
};
dma53: dma@53 {
compatible = "adi,dma2";
reg = <0x31026380 0x7F>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <106>;
};
dma54: dma@54 {
compatible = "adi,dma2";
reg = <0x31026300 0x7F>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
spu_securep_id = <106>;
};
*/
spi_cluster: dma@0x3102D000 {
compatible = "adi,dma-controller";
reg = <0x3102D000 0x1000>;
status = "okay";
#dma-cells = <1>;
spi0_tx: channel@22 {
adi,id = <22>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0>;
};
spi0_rx: channel@23 {
adi,id = <23>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0x80>;
};
spi1_tx: channel@24 {
adi,id = <24>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0x100>;
};
spi1_rx: channel@25 {
adi,id = <25>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0x180>;
};
spi2_tx: channel@26 {
adi,id = <26>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0x200>;
};
spi2_rx: channel@27 {
adi,id = <27>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0x280>;
};
};
sport_dma_cluster: dma@0x31023000 {
compatible = "adi,dma-controller";
reg = <0x31023000 0x1000>;
status = "okay";
#dma-cells = <1>;
sport0a: channel@0 {
adi,id = <0>;
adi,src-offset = <0>;
adi,skip-interrupts = <0>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
};
sport0b: channel@1 {
adi,id = <1>;
adi,src-offset = <0x80>;
adi,skip-interrupts = <0>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
};
sport1a: channel@2 {
adi,id = <2>;
adi,src-offset = <0>;
adi,skip-interrupts = <0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
};
sport1b: channel@3 {
adi,id = <3>;
adi,src-offset = <0x80>;
adi,skip-interrupts = <0>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
};
sport2a: channel@4 {
adi,id = <4>;
adi,src-offset = <0>;
adi,skip-interrupts = <0>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
};
sport2b: channel@5 {
adi,id = <5>;
adi,src-offset = <0x80>;
adi,skip-interrupts = <0>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
};
sport3a: channel@6 {
adi,id = <6>;
adi,src-offset = <0>;
adi,skip-interrupts = <0>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
};
sport3b: channel@7 {
adi,id = <7>;
adi,src-offset = <0x80>;
adi,skip-interrupts = <0>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
};
sport4a: channel@10 {
adi,id = <10>;
adi,src-offset = <0>;
adi,skip-interrupts = <0>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
};
sport4b: channel@11 {
adi,id = <11>;
adi,src-offset = <0x80>;
adi,skip-interrupts = <0>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
};
sport5a: channel@12 {
adi,id = <12>;
adi,src-offset = <0>;
adi,skip-interrupts = <0>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
};
sport5b: channel@13 {
adi,id = <13>;
adi,src-offset = <0x80>;
adi,skip-interrupts = <0>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
};
};
dma_cluster2: dma@0x31026000 {
compatible = "adi,dma-controller";
reg = <0x31026000 0x1000>;
status = "okay";
#dma-cells = <1>;
uart0_tx: channel@20 {
adi,id = <20>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0x80>;
};
uart0_rx: channel@21 {
adi,id = <21>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0>;
};
uart1_tx: channel@34 {
adi,id = <34>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0x180>;
};
uart1_rx: channel@35 {
adi,id = <35>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0x100>;
};
uart2_tx: channel@37 {
adi,id = <37>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0x280>;
};
uart2_rx: channel@38 {
adi,id = <38>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error";
adi,src-offset = <0x200>;
};
};
mdma: dma@0x3109a000 {
compatible = "adi,mdma-controller";
reg = <0x3109a000 0x1000>;
status = "okay";
sdma2: channel@40 {
adi,id = <40>;
// The destination interrupts are used for primary complete detection
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "complete", "error", "complete2", "error2";
adi,src-offset = <0>;
adi,dest-offset = <0x80>;
};
};
};
};
