From the processor hw reference manual page 222-223 I can see 18 steps to reset the SHARC core, but when I look at the core control driver in the linux distribution it seems to use only items from 11..18. There's no handshake to send the IDLE state using the RCU_MSG.
I'm facing few issues regarding the loadsharc_sc589 doing multiple load onto the same SHARC core. The first time it loads the LDR all goes well, but the second+ time it gets stuck wating from sharc core response. I guess once the SHARC core is running some code we are not able to reset it unil we send it to IDLE mode. Is that correct?
From the manual: 3. The master core sets the CCRx bit in message register and raises the SOFT0 software interrupt through the
SEC to the SHARC+ core (see Programming Examples for more information). I could not find the CCR bit in the RCU_MSG, am I looking at the wrong place? There's also something kind of a type in this section once it refers to a Core Reset Request bit (CRR) also not found in RCU_MSG register.
Thanks in advance!