2011-01-27 05:26:17 GPIO controlled SSEL deasserted too early by spi_bfin5xx?
Kolja Waschk (GERMANY)
Message: 97721
Hi,
I just noticed that spi_bfin5xx seems to deassert SSEL very early, maybe even too early. The following screenshot from a scope shows the end of a transfer at which SSEL is deasserted at the rising edge of the last clock pulse. I'd rather expect the signal to go high about the duration of one clock cycle later, at least somewhat after the last edge of the clock.
Signals are 1=SCK, 2=SSEL, 3=MOSI, 4=MISO
Kernel: unmodified from blackfin-linux-dist 2010R1-RC5
Board Settings:
enable_dma = 0
bits_per_word = 8
modalias = spidev
max_speed_hz = 3125000
bus_num = 0
chip_select = MAX_CTRL_CS + GPIO_PF4
mode = SPI_MODE_0
Transfer:
bits_per_word = 8
cs_change = 1
speed_hz = 10000
len = 5
tx_buf[] = 0x00 0x4c 0xa8 0x19 0x0b
Kolja
QuoteReplyEditDelete
2011-01-27 14:50:35 Re: GPIO controlled SSEL deasserted too early by spi_bfin5xx?
Mike Frysinger (UNITED STATES)
Message: 97727
hmm, yes, it does seem like the core code could run faster than the spi and deassert ssel too soon. our transfer logic simply fills the fifos and then returns. i dont see logic that polls the fifos to make sure they're empty before returning. we only have that logic at the start of a transfer.
try adding a call to bfin_spi_flush() in the bfin_spi_giveback() func just after the "msg->state = NULL" line.
QuoteReplyEditDelete
2011-03-15 08:42:59 Re: GPIO controlled SSEL deasserted too early by spi_bfin5xx?
Kolja Waschk (GERMANY)
Message: 98945
It helped for now to add the bfin_spi_flush() at the beginning of bfin_spi_cs_deactive(). Adding it in bfin_spi_giveback() wasn't sufficient. I haven't tested it much yet, though.. Kolja
early_cs.patch
QuoteReplyEditDelete
2011-07-07 16:38:54 Re: GPIO controlled SSEL deasserted too early by spi_bfin5xx?
Mike Frysinger (UNITED STATES)
Message: 102221
ive moved this to our tracker:
blackfin.uclinux.org/gf/tracker/6683