2011-07-12 09:22:13 queson on spidev transfer

Peter Lindner (AUSTRIA)

Message: 102365

hello...

currently i'm trying to send some data with my cm-bf527 via spi...

my problem is, that the spi-slave needs 16-bit words... so i what i want to achieve is, that after every 16-bits cs goes inactive and active again...

this is my current approach with spidev driver. but on oscilloscope it looks like the driver is activating cs and sending all of the data... not 16bit by 16bit.

how can i achieve this?

in my boardfile i have:

#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)

static struct bfin5xx_spi_chip spidev_chip_info = {

.enable_dma = 1,

.bits_per_word = 16,

};

#endif

this is my test program (modified spidev_test.c):

spi_test.c

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2011-07-12 10:31:26 Re: queson on spidev transfer

James Kosin (UNITED STATES)

Message: 102366

To do this, you need to change the tr structure you have to send only 16-bits or 2-bytes at a time and loop over the entire array size.

struct spi_ioc_transfer tr = {

.tx_buf = (unsigned long)tx,

.rx_buf = (unsigned long)NULL,

.len = ARRAY_SIZE(tx),

.delay_usecs = 50,

.speed_hz = speed,

.bits_per_word = bits,

.cs_change=1,

};

Set the .len to 2-bytes. Then in the loop, reset .tx_buf to point to the next 16-bits to deliver until the entire array is sent.

The code as it is you are telling it to send the whole array.

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2011-07-12 11:37:13 Re: queson on spidev transfer

Peter Lindner (AUSTRIA)

Message: 102368

hello james...

thank you for your help!

i'll try this...

but i don't understand for what reason do i need to set .bits_per_word??

regards peter

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2011-07-12 11:42:49 Re: queson on spidev transfer

Mike Frysinger (UNITED STATES)

Message: 102370

bfin5xx_spi_chip.bits_per_word is going away. you need to configure bits_per_word using the standard framework now. do it per-transfer, or set the default with the SPI_IOC_WR_BITS_PER_WORD ioctl.

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2011-07-12 11:49:04 Re: queson on spidev transfer

Peter Lindner (AUSTRIA)

Message: 102371

thank you for your advice...

but i don't get it, why i have to set this value... if the driver sends the whole array in one CS even though... what does this value change?

can you help me understanding the behaviour?

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2011-07-12 12:04:00 Re: queson on spidev transfer

Mike Frysinger (UNITED STATES)

Message: 102372

if the CS is held for the whole transfer, then the bits_per_word only affects byte swapping. 8bit transfers dont get swapped while 16bit do (depending on MSB vs LSB config).

and obviously you'll get a little better performance by using 16bit transfers instead of 8bit.

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2011-07-12 12:52:05 Re: queson on spidev transfer

Peter Lindner (AUSTRIA)

Message: 102373

ah now it's clear

thank you for your help!

best regards

peter

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2011-07-12 13:04:14 Re: queson on spidev transfer

Peter Lindner (AUSTRIA)

Message: 102374

as i noticed in another posting, i recognized a delay of ca. 200ns between activation of CS and the first databit.

is there a possibility to accelerate the sending?

i read about the option of using GPIO CS. does this eventually help?

for better understanding i added a scope picture (sorry for the bad scope settings but my usb scope doesn't get it better).

the white line is CS the pink one is the data line.

test

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2011-07-12 13:12:17 Re: queson on spidev transfer

Mike Frysinger (UNITED STATES)

Message: 102375

we might be able to shave it down a little, but we've never looked. and there will always be a delay when things are driven by software.

200ns sounds pretty good already ...

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2011-07-12 17:08:10 Re: queson on spidev transfer

Peter Lindner (AUSTRIA)

Message: 102376

oh... sorry... that was my fault...

thats not 200ns but 200us... for my understanding 200us is quite much, isn't it??

regards peter

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2011-07-12 17:41:13 Re: queson on spidev transfer

Mike Frysinger (UNITED STATES)

Message: 102377

200us is probably something we could improve upon, but again, it's not going to be perfect as it is the kernel driver which first executes code to set the CS level, and then the kernel code executes more code to do the transfers.

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2011-07-12 17:42:11 Re: queson on spidev transfer

Mike Frysinger (UNITED STATES)

Message: 102378

i guess the better question is, what timings would be "good enough" for you ? us getting it down to 180us probably doesnt matter that much if you're looking for 200ns :).

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2011-07-13 03:52:09 Re: queson on spidev transfer

Aaron Wu (CHINA)

Message: 102391

we have call bfin_spi_cs_active twice in our code, first in middle of bfin_spi_pump_messages, then in the end of bfin_spi_pump_messages we schedule a tasklet pump_transfers and call bfin_spi_cs_active again, then the first bit come out, so the long time is due to the tasklet schedule time. If this affect your hardware behavior we think it's safe for you to remove the first cs_active.

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2011-07-14 13:20:50 Re: queson on spidev transfer

Peter Lindner (AUSTRIA)

Message: 102408

thank you aaron for your explanation...

i'll re-check if this latency is too much for my needs...

but... i discovered another problem....

as you can see in the scope picture... before and after the transfer, the CS is also active... so i think this could be a problem, because i have two devices hanging on the spi...

so i think the level change at the end of a transfer could be interpreted as an falling edge by the device, couldn't be?

so... is there a chance to get CS always inactive (high) and only during transfers active?

regards peter

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2011-07-14 14:02:00 Re: queson on spidev transfer

Mike Frysinger (UNITED STATES)

Message: 102409

the CS being active before/after the transfer isnt a problem. it just needs to be inactive before doing a transfer to another device.

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2011-07-15 04:30:12 Re: queson on spidev transfer

Peter Lindner (AUSTRIA)

Message: 102433