2008-07-16 22:46:27 can not control PPI frame FS1 ?

edward jiang (CHINA)

Message: 58985

hi all:

PPI works under GP mode,output the datas,using 1 internal frame signal (FS1 ). The ppi_clk is supplied by a FPGA all the time.after i enabled the modules as the following order: 1) the DMA ; 2) the PPI; 3) the gptimer0 , i can get the datas in the FPGA, the datas is just ok , but i noticed that ,when fs1 became effective, 12 or more datas have been transmitted out of the ppi (the delayed ppi_clk number is random) . The timing plans is shown below .

Then , i changed the modules enable order: 1) the gptimer0 ; 2) the DMA ; 3) the PPI , then fs1 became effective before datas transmit out of the ppi about 2 or 3 ppi_clk ( the number of ppi_clk ahead of the datas seems random too ).The timing plans is shown below.

At last ,i changed the ppi_delay register to 10,hoping to get control of the fs1, but the fs1 still 12( or more ) ppi_clk later , or 2 ( or more ) ppi_clk earlier.it seems that the register does not work at all.

anyone has met the same problem before?please give me a hand.

thanks all.

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2008-07-17 10:52:29 Re: can not control PPI frame FS1 ?

Yi Li (CHINA)

Message: 59020

qq,

Since this is a HW question, I think you might get better answer if you post it at www.blackfin.org.