2008-08-18 04:59:02 how change a bf533 project to bf561?

Leslie Li (CHINA)

Message: 60561

Hi all

I have downloaded a mpeg4 decode project from AD website. Its Name is adi_mpeg4_decoder_BF_Rev3_1_0. But I need it run on adsp-bf561. So i don't use the default link file---mpeg4d_example.ldf. I use VDSP4.5 to autocreate a link file. The link file configured as followed:

mutil-core selection: Core A

System Heap: L3 external memory(SDRAM)

User Heap: L3 external memory(SDRAM)

System Stack: L3 external memory(SDRAM)

External Memory: L3 external memory(SDRAM)

the other configure is defult.

and the link file as followed:

ARCHITECTURE(ADSP-BF561)

SEARCH_DIR($ADI_DSP/Blackfin/lib)

// Workarounds are enabled, exceptions are disabled.

#define RT_LIB_NAME(x) lib ## x ## y.dlb

#define RT_LIB_NAME_EH(x) lib ## x ## y.dlb

#define RT_LIB_NAME_MT(x) lib ## x ## y.dlb

#define RT_LIB_NAME_EH_MT(x) lib ## x ## y.dlb

#define RT_OBJ_NAME(x) x ## y.doj

#define RT_OBJ_NAME_MT(x) x ## mty.doj

#define LIBS \

RT_LIB_NAME(small561) \

,RT_LIB_NAME_MT(io561) \

,RT_LIB_NAME_MT(c561) \

,RT_LIB_NAME_MT(event561) \

,RT_LIB_NAME_MT(x561) \

,RT_LIB_NAME_EH_MT(cpp561) \

,RT_LIB_NAME_EH_MT(cpprt561) \

,RT_LIB_NAME(f64ieee561) \

,RT_LIB_NAME(dsp561) \

,RT_LIB_NAME(sftflt561) \

,RT_LIB_NAME(etsi561) \

,RT_LIB_NAME(ssl561) \

,RT_LIB_NAME(drv561) \

,RT_LIB_NAME(rt_fileio561) \

$LIBS = LIBS;

/*$VDSG<insert-user-libraries-for-core-beginning> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-user-libraries-for-core-beginning> */

$LIBRARIES_CORE_A =

$LIBS {!sharing("MustShare")}

;

/*$VDSG<insert-user-libraries-for-core-end> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-user-libraries-for-core-end> */

$LIBRARIES_SHARED =

$LIBS

/*$VDSG<insert-user-libraries-shared> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-user-libraries-shared> */

;

$OBJECTS_CORE_A =

/*$VDSG<insert-user-objects-for-coreA-beginning> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-user-objects-for-coreA-beginning> */

".\Debug\mpeg4_decode_basiccrt.doj"

, RT_LIB_NAME(profile561)

, $COMMAND_LINE_OBJECTS {!DualCoreMem("CoreB")}

, "cplbtab561a.doj"

, RT_OBJ_NAME(crtn561)

/*$VDSG<insert-user-objects-for-coreA-end> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-user-objects-for-coreA-end> */

;

$OBJS_LIBS_INTERNAL_CORE_A =

/*$VDSG<insert-libraries-internal_coreA> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-libraries-internal_coreA> */

$OBJECTS_CORE_A{prefersMem("internal")}, $LIBRARIES_CORE_A{prefersMem("internal")}

/*$VDSG<insert-libraries-internal_coreA-end> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-libraries-internal_coreA-end> */

;

$OBJS_LIBS_NOT_EXTERNAL_CORE_A =

/*$VDSG<insert-libraries-not-external_coreA> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-libraries-not-external_coreA> */

$OBJECTS_CORE_A{!prefersMem("external")}, $LIBRARIES_CORE_A{!prefersMem("external")}

/*$VDSG<insert-libraries-not-external_coreA-end> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-libraries-not-external_coreA-end> */

;

/*$VDSG<insert-user-macros> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-user-macros> */

/*$VDSG<customise-async-macros> */

/* This code is preserved if the LDF is re-generated. */

#define ASYNC0_MEMTYPE RAM

#define ASYNC1_MEMTYPE RAM

#define ASYNC2_MEMTYPE RAM

#define ASYNC3_MEMTYPE RAM

/*$VDSG<customise-async-macros> */

MEMORY

{

** ADSP-BF561 MEMORY MAP.

** The known memory spaces are as follows:

** 0xFFE00000 - 0xFFFFFFFF Core MMR registers

** 0xFFC00000 - 0xFFDFFFFF System MMR (Shared)

** 0xFFB01000 - 0xFFBFFFFF

** 0xFFB00000 - 0xFFB00FFF Scratchpad

** 0xFFA14000 - 0xFFAF0000

** 0xFFA10000 - 0xFFA13FFF Instr SR/Ca

** 0xFFA08000 - 0xFFA0FFFF

** 0xFFA04000 - 0xFFA07FFF

** 0xFFA00000 - 0xFFA03FFF Instr SR

** 0xFF908000 - 0xFF9FFFFF

** 0xFF904000 - 0xFF907FFF Bank B SR/Ca

** 0xFF900000 - 0xFF903FFF Bank B SR

** 0xFF808000 - 0xFF8FFFFF

** 0xFF804000 - 0xFF807FFF Bank A SR/Ca

** 0xFF800000 - 0xFF803FFF Bank A SR

** 0xFF701000 - 0xFF7FFFFF

** 0xFF700000 - 0xFF700FFF Scratchpad

** 0xFF614000 - 0xFF6FFFFF

** 0xFF610000 - 0xFF613FFF Instr SR/Ca

** 0xFF608000 - 0xFF60FFFF

** 0xFF604000 - 0xFF607FFF

** 0xFF600000 - 0xFF603FFF Instr SR

** 0xFF508000 - 0xFF5FFFFF

** 0xFF504000 - 0xFF507FFF Bank B SR/Ca

** 0xFF500000 - 0xFF503FFF Bank B SR

** 0xFF408000 - 0xFF4FFFFF

** 0xFF404000 - 0xFF407FFF Bank A SR/Ca

** 0xFF400000 - 0xFF403FFF Bank A SR

** 0xFEB20000 - 0xFF3FFFFF

** 0xFEB00000 - 0xFEB1FFFF L2 Shared

** 0xEF004000 - 0xFEAFFFFF

** 0xEF002000 - 0xEF003FFF

** 0xEF001000 - 0xEF001FFF

** 0xEF000800 - 0xEF000FFF

** 0xEF000000 - 0xEF0007FF Boot ROM

** 0x30000000 - 0xEEFFFFFF

** 0x2C000000 - 0x2FFFFFFF Async 3

** 0x28000000 - 0x2BFFFFFF Async 2

** 0x24000000 - 0x27FFFFFF Async 1

** 0x20000000 - 0x23FFFFFF Async 0

** 0x00000000 - 0x1FFFFFFF SDRAM MEMORY (512MB)

MEM_L2_SRAM { TYPE(RAM) START(0xFEB10000) END(0xFEB1FFFF) WIDTH(8) }

MEM_ASYNC3 { TYPE(ASYNC3_MEMTYPE) START(0x2C000000) END(0x2FFFFFFF) WIDTH(8) }

MEM_ASYNC2 { TYPE(ASYNC2_MEMTYPE) START(0x28000000) END(0x2BFFFFFF) WIDTH(8) }

MEM_ASYNC1 { TYPE(ASYNC1_MEMTYPE) START(0x24000000) END(0x27FFFFFF) WIDTH(8) }

MEM_ASYNC0 { TYPE(ASYNC0_MEMTYPE) START(0x20000000) END(0x23FFFFFF) WIDTH(8) }

/* Maximum 256MB */

MEM_SDRAM_BANK0 { TYPE(RAM) START(0x00000004) END(0x00ffffff) WIDTH(8) }

MEM_SDRAM_BANK1 { TYPE(RAM) START(0x01000000) END(0x01ffffff) WIDTH(8) }

MEM_SDRAM_BANK2 { TYPE(RAM) START(0x02000000) END(0x02ffffff) WIDTH(8) }

MEM_SDRAM_BANK3 { TYPE(RAM) START(0x03000000) END(0x03ffffff) WIDTH(8) }

/*$VDSG<insert-new-memory-segments> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-new-memory-segments> */

} /* MEMORY */

PROCESSOR p0

{

MEMORY

{

MEM_L2_SRAM_A { TYPE(RAM) START(0xFEB08000) END(0xFEB0FFFF) WIDTH(8) }

MEM_A_L1_SCRATCH { TYPE(RAM) START(0xFFB00000) END(0xFFB00FFF) WIDTH(8) }

MEM_A_L1_CODE { TYPE(RAM) START(0xFFA00000) END(0xFFA03FFF) WIDTH(8) }

MEM_A_L1_DATA_B { TYPE(RAM) START(0xFF900000) END(0xFF907FFF) WIDTH(8) }

MEM_A_L1_DATA_A { TYPE(RAM) START(0xFF800000) END(0xFF807FFF) WIDTH(8) }

/*$VDSG<insert-new-memory-segments-for-CORE-A> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-new-memory-segments-for-CORE-A> */

} /* MEMORY */

OUTPUT($COMMAND_LINE_OUTPUT_FILE)

RESOLVE(start, 0xFFA00000)

KEEP(start,_main)

/*$VDSG<insert-user-ldf-commands-for-CORE-A> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-user-ldf-commands-for-CORE-A> */

SECTIONS

{

/* FEB1FC00->FEB1FFFF : Reserved in boot Phase for 2nd stage boot loader. */

RESERVE(___ssld=0xFEB1FC00, ___lssld = 0x400)

/*$VDSG<insert-new-sections-at-the-start-for-CORE-A> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-new-sections-at-the-start-for-CORE-A> */

scratchpad

{

INPUT_SECTION_ALIGN(4)

/*$VDSG<insert-input-sections-at-the-start-of-scratchpad-for-CORE-A> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-input-sections-at-the-start-of-scratchpad-for-CORE-A> */

} > MEM_A_L1_SCRATCH

L1_code

{

INPUT_SECTION_ALIGN(4)

__CORE = 0;

INPUT_SECTIONS($OBJECTS_CORE_A(L1_code) $LIBRARIES_CORE_A(L1_code))

/*$VDSG<insert-input-sections-at-the-start-of-l1_code> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-input-sections-at-the-start-of-l1_code> */

INPUT_SECTIONS($OBJECTS_CORE_A(VDK_ISR_code) $LIBRARIES_CORE_A(VDK_ISR_code))

INPUT_SECTIONS($OBJECTS_CORE_A(cplb) $LIBRARIES_CORE_A(cplb))

INPUT_SECTIONS($OBJECTS_CORE_A(cplb_code) $LIBRARIES_CORE_A(cplb_code))

INPUT_SECTIONS($OBJECTS_CORE_A(noncache_code) $LIBRARIES_CORE_A(noncache_code))

INPUT_SECTIONS($OBJS_LIBS_INTERNAL_CORE_A(program))

INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL_CORE_A(program))

INPUT_SECTIONS($OBJECTS_CORE_A(program) $LIBRARIES_CORE_A(program))

/*$VDSG<insert-input-sections-at-the-end-of-l1_code> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-input-sections-at-the-end-of-l1_code> */

} > MEM_A_L1_CODE

L1_data_a

{

INPUT_SECTION_ALIGN(4)

___l1_data_cache_a = 0;

INPUT_SECTIONS($OBJECTS_CORE_A(L1_data_a) $LIBRARIES_CORE_A(L1_data_a))

/*$VDSG<insert-input-sections-at-the-start-of-l1_data_a> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-input-sections-at-the-start-of-l1_data_a> */

INPUT_SECTIONS($OBJECTS_CORE_A{DualCoreMem("CoreA")}(cplb_data) $LIBRARIES_CORE_A{DualCoreMem("CoreA")}(cplb_data))

INPUT_SECTIONS($OBJECTS_CORE_A(cplb_data) $LIBRARIES_CORE_A(cplb_data))

INPUT_SECTIONS($OBJECTS_CORE_A(voldata) $LIBRARIES_CORE_A(voldata))

INPUT_SECTIONS($OBJECTS_CORE_A(constdata) $LIBRARIES_CORE_A(constdata))

INPUT_SECTIONS($OBJS_LIBS_INTERNAL_CORE_A(data1))

INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL_CORE_A(data1))

INPUT_SECTIONS($OBJECTS_CORE_A(data1) $LIBRARIES_CORE_A(data1))

INPUT_SECTIONS($OBJECTS_CORE_A(.edt) $LIBRARIES_CORE_A(.edt))

INPUT_SECTIONS($OBJECTS_CORE_A(.cht) $LIBRARIES_CORE_A(.cht))

/*$VDSG<insert-input-sections-at-the-end-of-l1_data_a> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-input-sections-at-the-end-of-l1_data_a> */

} > MEM_A_L1_DATA_A

bsz_L1_data_a ZERO_INIT

{

INPUT_SECTION_ALIGN(4)

INPUT_SECTIONS($OBJECTS_CORE_A(bsz) $LIBRARIES_CORE_A(bsz))

} > MEM_A_L1_DATA_A

L1_data_a_stack_heap

{

INPUT_SECTION_ALIGN(4)

} > MEM_A_L1_DATA_A

L1_data_b

{

INPUT_SECTION_ALIGN(4)

___l1_data_cache_b = 0;

INPUT_SECTIONS($OBJECTS_CORE_A(L1_data_b) $LIBRARIES_CORE_A(L1_data_b))

/*$VDSG<insert-input-sections-at-the-start-of-l1_data_b> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-input-sections-at-the-start-of-l1_data_b> */

INPUT_SECTIONS($OBJECTS_CORE_A(ctor) $LIBRARIES_CORE_A(ctor))

INPUT_SECTIONS($OBJECTS_CORE_A(ctorl) $LIBRARIES_CORE_A(ctorl))

INPUT_SECTIONS($OBJECTS_CORE_A(vtbl) $LIBRARIES_CORE_A(vtbl))

INPUT_SECTIONS($OBJECTS_CORE_A(.gdt) $LIBRARIES_CORE_A(.gdt))

INPUT_SECTIONS($OBJECTS_CORE_A(.gdtl) $LIBRARIES_CORE_A(.gdtl))

INPUT_SECTIONS($OBJECTS_CORE_A(.frt) $LIBRARIES_CORE_A(.frt))

INPUT_SECTIONS($OBJECTS_CORE_A(.rtti) $LIBRARIES_CORE_A(.rtti))

INPUT_SECTIONS($OBJECTS_CORE_A(.edt) $LIBRARIES_CORE_A(.edt))

INPUT_SECTIONS($OBJECTS_CORE_A(.cht) $LIBRARIES_CORE_A(.cht))

INPUT_SECTIONS($OBJS_LIBS_INTERNAL_CORE_A(data1))

INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL_CORE_A(data1))

INPUT_SECTIONS($OBJECTS_CORE_A(data1) $LIBRARIES_CORE_A(data1))

INPUT_SECTIONS($OBJECTS_CORE_A{DualCoreMem("CoreA")}(cplb_data) $LIBRARIES_CORE_A{DualCoreMem("CoreA")}(cplb_data))

INPUT_SECTIONS($OBJECTS_CORE_A(cplb_data) $LIBRARIES_CORE_A(cplb_data))

INPUT_SECTIONS($OBJECTS_CORE_A(voldata) $LIBRARIES_CORE_A(voldata))

INPUT_SECTIONS($OBJECTS_CORE_A(constdata) $LIBRARIES_CORE_A(constdata))

/*$VDSG<insert-input-sections-at-the-end-of-l1_data_b> */

/* Text inserted between these $VDSG comments will be preserved */

/*$VDSG<insert-input-sections-at-the-end-of-l1_data_b> */

} > MEM_A_L1_DATA_B

bsz_L1_data_b ZERO_INIT

{

INPUT_SECTION_ALIGN(4)

INPUT_SECTIONS($OBJS_LIBS_INTERNAL_CORE_A(bsz))

INPUT_SECTIONS($OBJS_LIBS_NOT_EXTERNAL_CORE_A(bsz))

INPUT_SECTIONS($OBJECTS_CORE_A(bsz) $LIBRARIES_CORE_A(bsz))

} > MEM_A_L1_DATA_B

L1_data_b_stack_heap

{

INPUT_SECTION_ALIGN(4)

} > MEM_A_L1_DATA_B

L2_sram_a

{

INPUT_SECTION_ALIGN(4)

INPUT_SECTIONS($OBJECTS_CORE_A(l2_sram) $LIBRARIES_CORE_A(l2_sram))

INPUT_SECTIONS($OBJECTS_CORE_A(VDK_ISR_code) $LIBRARIES_CORE_A(VDK_ISR_code))

/*$VDSG<insert-input-sections-at-the-start-of-l2_sram_a> */