2008-08-26 21:14:52 BF533 PPI driver...

alan pan (CHINA)

Message: 61139

I want to write a simple ppi driver for my own application. But can not enter DMA0 interrupt. It always says DMA error. Some code shows as below. I use BF533 EVM board. Could you please help me to have a analysis. What's the possible problem?

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static char buf[LEN];

static int ppi_open(struct inode *inode, struct file *filp) {

int ret;

// lets ask for the DMA channel

ret = request_dma(CH_PPI, "BF533_PPI_DMA");

if ( ret < 0 ) {

printk(" Unable to get DMA channel\n");

return -EFAULT;

}else {

// set the IRQ callback

set_dma_callback(CH_PPI, ppi_dma0_irq_handler, filp->private_data);

// turn off the DMA channel

disable_dma(CH_PPI);

// Enable Interrupts

set_dma_config(CH_PPI, 0x0B6);

// set address to drop data into

set_dma_start_addr(CH_PPI, (unsigned long)buf);

// set the transfer size in bytes

set_dma_x_count(CH_PPI,720);

// set the X modify ( dont worry about Y for this one )

set_dma_x_modify(CH_PPI,2);

// set the transfer size in bytes

set_dma_y_count(CH_PPI,576);

// set the X modify ( dont worry about Y for this one )

set_dma_y_modify(CH_PPI,2);

//clear dma status

bfin_write_DMA0_IRQ_STATUS(0x03);

clear_dma_irqstat(CH_PPI);

// sync the cores up

__builtin_bfin_ssync();

enable_dma(CH_PPI);

//The PPI is set to receive 576 lines for each frame

bfin_write_PPI_COUNT(719);

bfin_write_PPI_FRAME(576);

/* clear ppi status before enabling */

bfin_clear_PPI_STATUS();

bfin_write_PPI_CONTROL(0x0C1);

// sync the cores up

__builtin_bfin_ssync();

}

static irqreturn_t ppi_dma0_irq_handler(int irq, void *dev_id) {

printk("Interrupt entered! %d \n", c++);

clear_dma_irqstat(CH_PPI);

return IRQ_HANDLED;

}

struct file_operations ppi_driver_fops = {

owner: THIS_MODULE,

read: ppi_read,

write: NULL,

open: ppi_open,

release:ppi_release,

};

static int __init ppi_init(void){

int ret;

unsigned char tempReg;

printk("ppi driver initialize. \n");

//Setup of the async interface

bfin_write_EBIU_AMBCTL0(0x7bb07bb0);

bfin_write_EBIU_AMBCTL1(0x7bb07bb0);

bfin_write_EBIU_AMGCTL(0x01FF);

//EVM setting

*pFlashA_PortA_Out = 0x0; // clear data registers

*pFlashA_PortA_Dir = 0xFFFF; // set dir=output

tempReg = *pFlashA_PortA_Out;

*pFlashA_PortA_Out = tempReg | RST_7183 | PPICLK_ADV7183_SELECT;

tempReg = bfin_read_FIO_DIR();

bfin_write_FIO_DIR(tempReg | ADV7183_OE);

//Set the Blackfin pin PF2 to output enable the ADV7183 data bus

tempReg = bfin_read_FIO_FLAG_C();

bfin_write_FIO_FLAG_C(tempReg | ADV7183_OE);

bfin_write_PPI_CONTROL(0x0000);

bfin_clear_PPI_STATUS();

bfin_write_PPI_COUNT(0x0000);

bfin_write_PPI_FRAME(0x0000);

bfin_write_PPI_DELAY(0x0000);

ret = register_chrdev(250, "ppi_driver", &ppi_driver_fops);

if (ret < 0) {

printk(": chrdev registration failed. \n");

return ret;

}else {

printk(": register char device. \n");

}

return 0;

}

module_init(ppi_init);

.....................

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2008-08-26 21:24:42 Re: BF533 PPI driver...

Mike Frysinger (UNITED STATES)

Message: 61140

you are mucking with a lot of core registers that you should not. do not access port registers directly, use the GPIO/peripheral framework. do not muck with the async ebiu registers, use the kernel configuration for that.

if your purpose is simply to drive the ADV7183, then use the V4L framework in svn trunk as it supports the ADV7183

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2008-08-27 03:27:01 Re: BF533 PPI driver...

alan pan (CHINA)

Message: 61152

Actually those are not core registers. Just a adresses on output data bus. I use BF533 EVM board. Before video capturing, ADV7183 should be enabled(Just pull OE to low, select ppi clock). By default, ADV7183 will output itu656 video streaming.

You said V4L framework? But I can not find the exactly code on ADV7183 enable of BF533 EVM board. So could you please give me a guidence of that?

I also comment out the async ebiu registers setting, i.e., use the kernel configuration for that. But the result is the same.

Thanks.

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2008-08-27 16:26:45 Re: BF533 PPI driver...

Mike Frysinger (UNITED STATES)

Message: 61196

they are core registers that are maintained by the core Blackfin code ... where the device lives is irrelevant

all V4L stuff can be found in svn trunk and in the documentation wiki

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2008-08-27 21:09:19 Re: BF533 PPI driver...

alan pan (CHINA)

Message: 61208

Add the define of those "core registers":

#define pFlashA_PortA_Dir ((volatile unsigned short *)0x20270006)

#define pFlashA_PortA_Out ((volatile unsigned char *)0x20270004)

They are in ASYNC MEMORY.

So is there any registers you think they are core registers? Or I've misunderstood what's you meaning?

I've read the code of v4l. But I don't think they are working BF533 EVM board. So it is not related with ADV7183 enable on EVM board.

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2008-08-28 02:44:55 Re: BF533 PPI driver...

Mike Frysinger (UNITED STATES)

Message: 61224

look at all the bfin_write_* calls you're making. you should only be hitting DMA/PPI registers -- the rest are wrong.

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2008-08-28 21:50:39 Re: BF533 PPI driver...

alan pan (CHINA)

Message: 61291

Could you please give a more detailed explanation? and how to correct them? I once developed a PPI driver in uclinux kernal 2.4, it's not a problem for such code.

Thanks a lot.

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2008-08-28 22:03:43 Re: 回复： Re: BF533 PPI driver...

Robin Getz (UNITED STATES)

Message: 61293

Alan:

2.6 != 2.4

We are not doing thing the proper way - this means there are resource managers to manage the hardware so all the drivers play well together - the key part of this working - is that the resource manager assumes that it has 100% of the complete hardware.

You making changes behind the resource managers back is a sure fire way for random kernel crashes.

-Robin

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2008-08-28 22:53:17 Re: BF533 PPI driver...

Mike Frysinger (UNITED STATES)

Message: 61300

if you need to allocate pins for peripheral function, use the peripheral API. if you need to allocate pins for GPIO function, use the GPIO API.

you can search the wiki for documentation, or look at other PPI drivers in the current kernel.

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2008-08-29 04:48:26 回复： Re: BF533 PPI driver...

alan pan (CHINA)

Message: 61317