2008-11-16 16:12:56 HELP EZ KIT 548 0x2400000 memory dump
D V (ITALY)
Message: 65351
Can anyone post a memory dump of address 0x24000000 async mem of the board Ez-KIT lite 548?
I have a custom board with a blackfin 548 and the ethernet chip lan9218 on /AMCS1 but the ethernet test fails and reading with the VisualDsp the memory area i get only 00. The Async mem registers are in the default mode and the banks are all enabled.
Async regs values i m using
bank enable 00000000e
CTL0 FFC2FFC2
CTL1 FFC2FFC2
MODE 000000000
FCTL 00000006
PORTH_MUX is 01 function and PORTH_FER is 1 in the related bit for A4 A5 A6 A7 ....
So if someone can post a dump of the ethernet lan9218 chip area and async regs values then i can see the right values.
THANKS a lot
bye
emag
PS i added this message in the news discussion also i m sorry but i dunno of to remove it.
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2008-11-17 10:09:30 Re: HELP EZ KIT 548 0x2400000 memory dump
Kyle Schlansker (UNITED STATES)
Message: 65378
We had the same issue, initially, with our custom board. We kept reading 0's when trying to read the ID REV field of the ethernet chip (the value at offset 0x50h or 0x2400050). It turned out we needed to tie the EEDIO pin to ground (or, if you're using eeprom, then just use a pull down). Could this be your problem too?
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2008-11-17 10:27:09 Re: HELP EZ KIT 548 0x2400000 memory dump
D V (ITALY)
Message: 65380
Yep the ID_REV and all other values are 00. I have already checked the EEDIO that is pulled down. But i will recheck it because the resistor can be not connected properly.
Thanks a lot Kyle
bye
emag
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2008-11-22 15:57:15 Re: HELP EZ KIT 548 0x2400000 memory dump
D V (ITALY)
Message: 65722
Hi Kyle, now the BYTE TEST is ok. But some time i read wrong data from the chip and software reset seems not to work.
In the VDD_CORE voltage i have 1.26V and not 1.8V.
What the voltage VDD_CORE & VDD_PLL in your board?
Thanks a lot
bye
emag
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2008-11-24 10:21:11 Re: HELP EZ KIT 548 0x2400000 memory dump
Kyle Schlansker (UNITED STATES)
Message: 65761
VDD_CORE should definitely be at 1.8. Have you measured 3.3v going into the chip?
VDD_PLL is also 1.8, but that is an output of a separate internal regulator. There is a design note saying to make sure and not tie the VDD_CORE and VDD_PLL lines together as they are driven by two separate regulators.