2009-12-31 07:17:42     bf531 silicon revision 0.5 dcplb cache problem

2009-12-31 07:17:42     bf531 silicon revision 0.5 dcplb cache problem

victor fang (CHINA)

Message: 84104   

I  migrate my platform from 2007R1.1-RC3 to 2009R1-RC6.  I encountered a problem with ethernet driver.  The CPU I used is BF531 0.5, and the ethernet is attached to AMS2.

If I configure the Kernel with silicon revision 0.5,  sometime ethernet cannot be detected, or there is huge delay  (around 1 second)  when ping another ip address. This problem can be overcomed temporarily by disabling ICACHE in kernel config.

After more inspection, I found if I configure the Kernel with silicon revision 0.4, everything is ok.

Below is cplbinfo under 2007R1.1 and 2009R1 respectively:

# 2009R1 with kernel config of silicon revision=5

root:/proc/cplbinfo/cpu0> cat icplb

ICPLBs are disabled: 0x1

Index   Address         Data    Size    U/RD    U/WR    S/WR    Switch

0       0x00000000      00083   1K      N       N       N       N

1       0x00000000      31205   4M      Y       N       N       N

2       0xffa08000      30007   4M      Y       N       N       N

3       0x00000000      00000   1K      N       N       N       Y

4       0x00000000      00000   1K      N       N       N       Y

5       0x00000000      00000   1K      N       N       N       Y

6       0x00000000      00000   1K      N       N       N       Y

7       0x00000000      00000   1K      N       N       N       Y

8       0x00000000      00000   1K      N       N       N       Y

9       0x00000000      00000   1K      N       N       N       Y

10      0x00000000      00000   1K      N       N       N       Y

11      0x00000000      00000   1K      N       N       N       Y

12      0x00000000      00000   1K      N       N       N       Y

13      0x00000000      00000   1K      N       N       N       Y

14      0x00000000      00000   1K      N       N       N       Y

15      0x00000000      00000   1K      N       N       N       Y

root:/proc/cplbinfo/cpu0> cat dcplb

DCPLBs are enabled: 0x100b

Index   Address         Data    Size    U/RD    U/WR    S/WR    Switch

0       0x00000000      00083   1K      N       N       N       N

1       0x00000000      3109d   4M      Y       Y       Y       N

2       0x01e00000      2109d   1M      Y       Y       Y       Y

3       0x01c00000      2109d   1M      Y       Y       Y       Y

4       0x01f00000      2009d   1M      Y       Y       Y       Y

5       0x01d00000      2109d   1M      Y       Y       Y       Y

6       0x20300000      2009d   1M      Y       Y       Y       Y

7       0x20200000      2009d   1M      Y       Y       Y       Y

8       0x01800000      3109d   4M      Y       Y       Y       Y

9       0x00000000      00000   1K      N       N       N       Y

10      0x00000000      00000   1K      N       N       N       Y

11      0x00000000      00000   1K      N       N       N       Y

12      0x00000000      00000   1K      N       N       N       Y

13      0x00000000      00000   1K      N       N       N       Y

14      0x00000000      00000   1K      N       N       N       Y

15      0x00000000      00000   1K      N       N       N       Y

root:/proc/cplbinfo/cpu0>

# 2007R1.1 with kernel config of silicon revision=5

root:/proc> cat cplbinfo

------------------ CPLB Information ------------------

Instrction CPLB entry:

Address         Data    Size    Valid   Locked  Swapin  iCount  oCount

0x00000000      0x00283 1K      Y       Y        0      0       0

0xffa08000      0x30007 4M      Y       Y        1      0       0

0x00000000      0x31287 4M      Y       Y        2      0       0

0x00400000      0x31205 4M      Y       N        3      0       0

0x00800000      0x31205 4M      Y       N        4      0       0

0x00c00000      0x31205 4M      Y       N        5      0       0

0x01000000      0x31205 4M      Y       N        6      0       0

0x01400000      0x31205 4M      Y       N        7      0       0

0x01800000      0x31205 4M      Y       N        8      0       0

0x01c00000      0x21205 1M      Y       N        9      0       0

0x01d00000      0x21205 1M      Y       N       10      0       0

0x01e00000      0x21205 1M      Y       N       11      0       0

Unused/mismatched CPLBs:

12: 0x00000000  0x00000 1K      N       N

13: 0x00000000  0x00000 1K      N       N

14: 0x00000000  0x00000 1K      N       N

15: 0x00000000  0x00000 1K      N       N

Data CPLB entry:

Address         Data    Size    Valid   Locked  Swapin  iCount  oCount

0x00000000      0x00283 1K      Y       Y        0      0       2

0x00000000      0x3d29f 4M      Y       Y        1      0       0

0x00400000      0x3d29d 4M      Y       N        2      0       0

0x00800000      0x3d29d 4M      Y       N        3      0       0

0x00c00000      0x3d29d 4M      Y       N        4      0       0

0x01000000      0x3d29d 4M      Y       N        5      0       0

0x01400000      0x3d29d 4M      Y       N        6      0       0

0x01800000      0x3d29d 4M      Y       N        7      0       0

0x01c00000      0x2d29d 1M      Y       N        8      0       0

0x01d00000      0x2d29d 1M      Y       N        9      0       0

0x01e00000      0x2d29d 1M      Y       N       10      0       0

0x01f00000      0x2029d 1M      Y       N       11      0       0

0x20000000      0x2029d 1M      Y       N       -1      0       0

0x20100000      0x2029d 1M      Y       N       -1      0       0

0x20200000      0x2029d 1M      Y       N       15      1       0

0x20300000      0x2029d 1M      Y       N       14      1       0

Unused/mismatched CPLBs:

12: 0x00000000  0x00000 1K      N       N

13: 0x00000000  0x00000 1K      N       N

So I think this problem is relative to ANOMALY_05000158. It seems BF531 0.5 does not resolve bug of ANOMALY_05000158. Does any guy help me to confirm this problem? Is there any patch for 2009R1-RC6?

Thanks.

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2009-12-31 12:24:31     Re: bf531 silicon revision 0.5 dcplb cache problem

Robin Getz (UNITED STATES)

Message: 84106   

Victor:

I don't think this sounds like 158 - the issue would appear as random crashes at boot, or kernel load.

158 is after a DMA to the L1 instruction memory, a data cache fill to the corresponding port may get corrupted data. DMA to L1 instruction only happens in U-Boot, and when the kernel loads - otherwise nothing touches L1 instruction.

Your description is way beyond that point.

-Robin

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2010-01-03 22:16:35     Re: bf531 silicon revision 0.5 dcplb cache problem

Yi Li (CHINA)

Message: 84148   

Can you try 2009R1.1-RC4: https://blackfin.uclinux.org/gf/project/uclinux-dist/frs

I added a tracker so someone can have a look: https://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=5804

-Yi

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2010-01-12 06:35:59     Re: bf531 silicon revision 0.5 dcplb cache problem

victor fang (CHINA)

Message: 84458   

Thanks all.

I did more test in these days. If I configure the Kernel with silicon revision 0.4, the problem cannot be resolved completely. The ethernet can be detected and work all time, but there is 8% packet lost.

Furthermore, I upgraded kernel to 2009R1.1-RC4, this problem still exists.

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2010-01-12 06:56:51     Re: bf531 silicon revision 0.5 dcplb cache problem

Michael Hennerich (GERMANY)

Message: 84459    What Ethernet controller are you using?

How did you configure the EBIU settings for AMS2?

-Michael

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2010-01-12 07:33:55     Re: bf531 silicon revision 0.5 dcplb cache problem

victor fang (CHINA)

Message: 84461   

#

# EBIU_AMGCTL Global Control

#

CONFIG_C_AMCKEN=y

CONFIG_C_CDPRIO=y

# CONFIG_C_AMBEN is not set

# CONFIG_C_AMBEN_B0 is not set

# CONFIG_C_AMBEN_B0_B1 is not set

# CONFIG_C_AMBEN_B0_B1_B2 is not set

CONFIG_C_AMBEN_ALL=y

#

# EBIU_AMBCTL Control

#

CONFIG_BANK_0=0x7BB0

CONFIG_BANK_1=0xFFC2

CONFIG_BANK_2=0xFFC2

CONFIG_BANK_3=0x7BB0

EBIU for AMS2 0xFFC2  is as same as in 2007R1.1-RC3. Ethernet  is KSZ8842.

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2010-01-12 08:08:43     Re: bf531 silicon revision 0.5 dcplb cache problem

Michael Hennerich (GERMANY)

Message: 84463    Did System Clock (SLCK) and Core Clock (CCLK) change?

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2010-01-13 02:09:22     Re: bf531 silicon revision 0.5 dcplb cache problem

victor fang (CHINA)

Message: 84499   

  root:/proc> cat cpuinfo

processor       : 0

vendor_id       : Analog Devices

cpu family      : 0x27a5

model name      : ADSP-BF531 400(MHz CCLK) 100(MHz SCLK) (mpu off)

stepping        : 6

cpu MHz         : 400.000/100.000

bogomips        : 796.67

Calibration     : 398336000 loops

cache size      : 16 KB(L1 icache) 16 KB(L1 dcache-wb) 0 KB(L2 cache)

dbank-A/B       : cache/sram

icache setup    : 4 Sub-banks/4 Ways, 32 Lines/Way

dcache setup    : 1 Super-banks/4 Sub-banks/2 Ways, 64 Lines/Way

board name      : ADI BF533-STAMP

board memory    : 32768 kB (0x00000000 -> 0x02000000)

kernel memory   : 31736 kB (0x00001000 -> 0x01eff000)

SCLK 100Mhz is as same as in 2007R1.1-RC3. I do think this problem is relevant to cache, as I can disable Icache to overcome it.

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2010-01-13 13:51:05     Re: bf531 silicon revision 0.5 dcplb cache problem

Robin Getz (UNITED STATES)

Message: 84547   

Victor:

The problem might be related to cache - but it is most likely not ANOMALY_05000158.

We will need to get a 0.6 533 and try things out.

-Robin

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2010-01-14 03:10:00     Re: bf531 silicon revision 0.5 dcplb cache problem

victor fang (CHINA)

Message: 84558   

Hi Robin,

After test today, I found this problem didn't exist no more. I didn't change any ethernet driver code or the kernel configuretion, but a jffs2 problem. The rootfs was mounted as read only before, but is mounted read/write now. However there is another jffs2 problem as I reported to   blackfin.uclinux.org/gf/forummessage/84532.

I really don't know the exact reason of this problem.

Thanks.