2008-10-10 10:30:52 L R Channel Swap in BF533
Appalayagari Sreedhar (INDIA)
Message: 63419
Hi,
Does anyone has implemented workaround for the anamoly L R Channel Swap in BF533.
05000265 -
- Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks:
Best Regards, Sreedhar.
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2008-10-10 12:07:08 Re: L R Channel Swap in BF533
Robin Getz (UNITED STATES)
Message: 63433
Sreedhar:
rgetz@imhotep:~/blackfin/trunk/uClinux-dist/linux-2.6.x> grep 265 include/asm-blackfin/mach-*/anomaly.h
include/asm-blackfin/mach-bf527/anomaly.h:#define ANOMALY_05000265 (1)
include/asm-blackfin/mach-bf533/anomaly.h:#define ANOMALY_05000265 (1)
include/asm-blackfin/mach-bf537/anomaly.h:#define ANOMALY_05000265 (1)
include/asm-blackfin/mach-bf548/anomaly.h:#define ANOMALY_05000265 (1)
include/asm-blackfin/mach-bf561/anomaly.h:#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
But, there are no uses of that in the kernel - since all the wordarounds are HARDWARE workarounds, or done in U-Boot (u-boot-1.1.6/cpu/blackfin/initcode.c)
#ifndef CONFIG_PLL_CTL_VAL
# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
#endif
So, I think it is taken care of.
-Robin
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2008-10-13 02:39:30 Re: L R Channel Swap in BF533
Appalayagari Sreedhar (INDIA)
Message: 63514
Hi Robin,
Thankyou very much.
I am working with the u-boot version u-boot 1.1.6 2007 R1.
I could not find this macro CONFIG_PLL_CTL_VAL in this version of u-boot.
PLL_CTL value is configured in the file. cpu/bf533/init_sdram.S
Macro CONFIG_PLL_CTL_VAL is found in the latest u-boot 1.1.6 2008 R1.5. and also the work around.
Problem is now i can not change the u-boot, Is there any way I can do the work around in the kernel, I hope there will be a way to solve this problem.
can you please help me to solve this problem.
Best Regards, Sreedhar.
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2008-10-13 02:45:12 Re: L R Channel Swap in BF533
Mike Frysinger (UNITED STATES)
Message: 63515
you have all the source code and you see the required change. so just make it in your own version.