[#3985] my bf54x board can't be in low clocking
Submitted By: Meihui Fan
2008-03-25 00:01:14 Close Date
Closed Fixed In Release:
Found In Release:
Kernel Functions Board:
BF549 Silicon Revision:
Is this bug repeatable?:
Uboot version or rev.:
svn trunk(1.1.6) Toolchain version or rev.:
App binary format:
Summary: my bf54x board can't be in low clocking
When I try to re-program clocks in low rate while kernel boots, it seems my bf54x board (customized reference to BF548-EZKIT) would hang or trigger double-fault exception. e.g.:
--- Clock/PLL Setup
(12000000) Crystal Frequency in Hz
[*] Re-program Clocks while Kernel boots?
[ ] Bypass PLL
[ ] Half Clock In
(10) VCO Multiplier
Core Clock Divider (1) --->
(2) System Clock Divider
The board is clocking in 528/132 MHz from U-Boot.
I did many tests, and I believe the matter is the `System Clock Divider'. While the board works well on VCOM=44 and SCLKD=4, it involved in double-fault exception on VCOM=44 and SCLKD=12.
--- Sonic Zhang 2008-03-28 06:19:46
--- Meihui Fan 2008-04-01 04:48:37
The latest svn trunk is still not works on my board...
How's going on the ezkit?
--- Robin Getz 2008-04-20 21:50:11
The DDR min speed specified by JEDEC is 84MHz - you have it set for 60.
--- Robin Getz 2008-07-20 11:14:18
Closing since it seems to be fixed, and no comments in months.
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