[#4412] BF533 + 0.5 silicon + MPU + UART PIO -> crash

Submitted By: Mike Frysinger

Open Date

2008-09-05 13:05:41 Close Date

2008-11-14 06:20:42

Priority:

Medium Assignee:

Michael Hennerich

Status:

Closed Fixed In Release:

N/A

Found In Release:

N/A Release:

2008R1.5 or trunk

Category:

N/A Board:

N/A

Processor:

BF533 Silicon Revision:

0.5

Is this bug repeatable?:

Yes Resolution:

Fixed

Uboot version or rev.:

Toolchain version or rev.:

App binary format:

N/A

Summary: BF533 + 0.5 silicon + MPU + UART PIO -> crash

Details:

if you configure the kernel for a BF533-EZKIT with 0.5 silicon, and then enable the MPU and change the UART from DMA to PIO mode, the system crashes. leaving the UART in DMA mode and it boots fine.

here is the crash message from svn trunk:

IP-Config: Complete:

device=eth0, addr=192.168.0.15, mask=255.255.255.0, gw=192.168.0.1,

host=bf533-ezkit, domain=, nis-domain=(none),

bootserver=192.168.0.2, rootserver=192.168.0.2, rootpath=

eth0: link up, 100Mbps, full-duplex, lpa 0x45E1

_____________________________________

System MMR Error

- An error occurred due to an invalid access to an System MMR location

Possible reason: a 32-bit register is accessed with a 16-bit instruction

or a 16-bit register is accessed with a 32-bit instruction.

Kernel OOPS in progress

HW Error context

CURRENT PROCESS:

COMM=sh PID=128

TEXT = 0x00000000-0x00000000 DATA = 0x00000000-0x00000000

BSS = 0x00000000-0x00000000 USER-STACK = 0x00000000

return address: [0xffa01524]; contents of:

0xffa01500: ???? ???? ???? ???? ???? ???? ???? ????

0xffa01510: ???? ???? ???? ???? ???? ???? ???? ????

0xffa01520: ???? ???? [????] ???? ???? ???? ???? ????

0xffa01530: ???? ???? ???? ???? ???? ???? ???? ????

SEQUENCER STATUS: Not tainted

SEQSTAT: 0000a03f IPEND: 8030 SYSCFG: 0006

HWERRCAUSE: 0x2

EXCAUSE : 0x3f

physical IVG15 asserted : <0xffa00d88> { _evt_system_call + 0x0 }

logical irq 6 mapped : <0xffa0036c> { _timer_interrupt + 0x0 }

logical irq 14 mapped : <0x000a9350> { _bfin_rtc_interrupt + 0x0 }

logical irq 21 mapped : <0x0009b158> { _bfin_serial_rx_int + 0x0 }

logical irq 22 mapped : <0x0009b2ec> { _bfin_serial_tx_int + 0x0 }

logical irq 42 mapped : <0x000a21e4> { _smc_interrupt + 0x0 }

RETE: <0x00000000> { _run_init_process + 0xfffff000 }

RETN: <0x01b9fd80> /* kernel dynamic memory */

RETX: <0xffa01524> { _memset + 0x28 }

RETS: <0x0003b096> { _do_mmap_pgoff + 0x7a2 }

PC : <0xffa01524> { _memset + 0x28 }

PROCESSOR STATE:

R0 : 01180000 R1 : 00000000 R2 : 00000000 R3 : 011e9000

R4 : 01180000 R5 : 00000000 R6 : 00000002 R7 : 00000004

P0 : 01181d68 P1 : 0001a400 P2 : 011e9000 P3 : 01b99ec0

P4 : 00069000 P5 : 00069000 FP : 00069000 SP : 01b9fca4

LB0: ffa01524 LT0: ffa01524 LC0: 00019ca6

LB1: 00016816 LT1: 00016800 LC1: 00000000

B0 : 00000000 L0 : 00000000 M0 : 00000000 I0 : 00000001

B1 : 00000000 L1 : 00000000 M1 : 00000000 I1 : 01e79080

B2 : 00000000 L2 : 00000000 M2 : 00000000 I2 : 00000000

B3 : 00000000 L3 : 00000000 M3 : 00000000 I3 : 00000000

A0.w: 00000000 A0.x: 00000000 A1.w: 00000000 A1.x: 00000000

USP : 01bb8d28 ASTAT: 00002021

Hardware Trace:

0 Target : <0x0000476c> { _trap_c + 0x0 }

Source : <0xffa00cb8> { _evt_ivhw + 0x8c } CALL pcrel

1 Target : <0xffa00c9a> { _evt_ivhw + 0x6e }

Source : <0xffa00c96> { _evt_ivhw + 0x6a } IF !CC JUMP

2 Target : <0xffa00c2c> { _evt_ivhw + 0x0 }

Source : <0xffa00c28> { __common_int_entry + 0xd8 } RTI

3 Target : <0xffa00bc6> { __common_int_entry + 0x76 }

Source : <0xffa00a14> { _return_from_int + 0x58 } RTS

4 Target : <0xffa00a14> { _return_from_int + 0x58 }

Source : <0xffa009ea> { _return_from_int + 0x2e } IF !CC JUMP

5 Target : <0xffa009bc> { _return_from_int + 0x0 }

Source : <0xffa00bc2> { __common_int_entry + 0x72 } CALL pcrel

6 Target : <0xffa00bc0> { __common_int_entry + 0x70 }

Source : <0xffa00338> { _asm_do_IRQ + 0x6c } RTS

7 Target : <0xffa00330> { _asm_do_IRQ + 0x64 }

Source : <0x00013058> { _irq_exit + 0x2c } RTS

8 Target : <0x0001303e> { _irq_exit + 0x12 }

Source : <0xffa0045c> { _ex_dcplb_miss + 0xdc } RTX

9 Target : <0xffa003ee> { _ex_dcplb_miss + 0x6e }

Source : <0x00009b64> { _dcplb_miss + 0x1d0 } RTS

10 Target : <0x00009acc> { _dcplb_miss + 0x138 }