[#4671] add workaround for anomaly 05000412

Submitted By: Mike Frysinger

Open Date

2008-11-25 18:56:46 Close Date

2009-03-03 03:19:45

Priority:

Medium Assignee:

Graf Yang

Status:

Closed Fixed In Release:

N/A

Found In Release:

N/A Release:

Category:

N/A Board:

N/A

Processor:

BF561 Silicon Revision:

Is this bug repeatable?:

Yes Resolution:

Fixed

Uboot version or rev.:

Toolchain version or rev.:

09r1

App binary format:

N/A

Summary: add workaround for anomaly 05000412

Details:

the bf561 has an anomaly when using TESTSET for L2 and when data cache is in writeback mode which we'll need a workaround for

DESCRIPTION:

If the TESTSET instruction is used to operate on L2 memory and there is data in external memory that is cached using writeback mode, the

data in external memory and/or L2 memory can be corrupted. This issue applies equally to both cores.

In order to see this issue, a single core must initiate both the TESTSET and the cache access. The problem is not encountered if one core

issues a TESTSET and the other core issues the cache line request. Similarly, the problem does not manifest if the TESTSET and the cache

access are to the same memory space (L2/L2 or external/external).

The corrupted data will be seen in L2 and/or external memory when the problem occurs.

WORKAROUND:

Either do not use writeback cache or precede the TESTSET instruction with an SSYNC instruction. If preceding the TESTSET instruction by

an SSYNC instruction, do the following:

CLI R0;

R1 = [P0]; /* If the address that P0 points to is not covered by an installed CPLB,

perform a dummy read to make sure CPLB is installed */

NOP;

SSYNC;

TESTSET (P0);

STI R0;

The problem is also avoided if the TESTSET instruction is used to operate on a non-cacheable location that is in the same space as the

writeback data. For example, the TESTSET instruction operates on non-cacheable external memory, and the writeback cacheable location

is also in external memory.

Follow-ups

--- Sonic Zhang 2008-11-25 22:28:35

SMP kernel doesn't use writeback cache. This walkaround only affects UP kernel

with writeback cache enabled for DRAM on bf561 and L2 SRAM is not cached and

atomic data are put into L2.

--- Mike Frysinger 2008-11-26 02:15:46

the Kconfig allows for write through or write back to be selected for SMP.

however, the issue affects both cores and the use of testset. plus the fix is

pretty much exactly the same as the ssync/csync workarounds, so simply copying

those should be relatively trivial.

--- Graf Yang 2008-12-12 04:25:41

Now the Kconfig has disallowed people use write back cache when SMP for BF561

opened.

So far there are two lines code (arch/blackfin/mach-bf561/atomic.S) which only

used by SMP have used TESTSET. So these codes not affected by this anomaly.

I have add this anomaly to the arch/blackfin/mach-bf5xx/include/mach/anomaly.h

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