[#5933] BF561-EZKIT SMP kernel can not wake up from standby mode by uart interrupt

Question

Accepted Answer

[#5933] BF561-EZKIT SMP kernel can not wake up from standby mode by uart interrupt

Submitted By: Vivi Li

Open Date

2010-02-26 03:10:02 Close Date

2010-03-22 05:37:06

Priority:

Medium High Assignee:

Graf Yang

Status:

Closed Fixed In Release:

N/A

Found In Release:

2010R1 Release:

Category:

Drivers Board:

N/A

Processor:

BF561 Silicon Revision:

Is this bug repeatable?:

Yes Resolution:

Fixed

Uboot version or rev.:

Toolchain version or rev.:

gcc4.3-2010_Jan_22-svn3815

App binary format:

N/A

Summary: BF561-EZKIT SMP kernel can not wake up from standby mode by uart interrupt

Details:

BF561-EZKIT SMP kernel can not wake up from standby mode by uart interrupt.

The last passed version:

--

kernel: Linux release 2.6.32.7-ADI-2010R1-pre-svn8261, build #72 SMP Sun Jan 31 15:44:59 GMT 2010

toolchain: bfin-uclinux-gcc release gcc version 4.3.4 (ADI-trunk/svn-3815)

user-dist: release svn-9426, build #864 Sun Jan 31 15:43:34 GMT 2010

--

The first failed version:

--

kernel: Linux release 2.6.32.7-ADI-2010R1-pre-svn8265, build #76 SMP Wed Feb 3 23:05:57 GMT 2010

toolchain: bfin-uclinux-gcc release gcc version 4.3.4 (ADI-trunk/svn-3815)

user-dist: release svn-9431, build #915 Wed Feb 3 23:04:42 GMT 2010

--

Linux version 2.6.32.7-ADI-2010R1-pre-svn8265 (test@uclinux65-561-SMP) (gcc version 4.3.4 (ADI-trunk/svn-3815) ) #76 SMP Wed Feb0

register early platform devices

bootconsole [early_shadow0] enabled

bootconsole [early_BFuart0] enabled

early printk enabled on early_BFuart0

Board Memory: 64MB

Kernel Managed Memory: 64MB

Memory map:

fixedcode = 0x00000400-0x00000490

text = 0x00001000-0x0010f260

rodata = 0x0010f260-0x00162d4c

bss = 0x00163000-0x001755a8

data = 0x001755c0-0x00188000

stack = 0x00186000-0x00188000

init = 0x00188000-0x006b7000

available = 0x006b7000-0x03f00000

DMA Zone = 0x03f00000-0x04000000

Hardware Trace Active and Enabled

Boot Mode: 0

Reset caused by Software reset

Compiled for ADSP-BF561 Rev 0.5

Blackfin Linux support by http://blackfin.uclinux.org/

Processor Speed: 600 MHz core clock and 100 MHz System Clock

NOMPU: setting up cplb tables

Instruction Cache Enabled for CPU0

External memory: cacheable in instruction cache

L2 SRAM : uncacheable in instruction cache

Data Cache Enabled for CPU0

External memory: cacheable (write-through) in data cache

L2 SRAM : uncacheable in data cache

Built 1 zonelists in Zone order, mobility grouping off. Total pages: 16002

Kernel command line: root=/dev/mtdblock0 rw clkin_hz=30000000 earlyprintk=serial,uart0,57600 console=ttyBF0,57600 ip=10.100.4.50f

PID hash table entries: 256 (order: -2, 1024 bytes)

Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)

Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)

Memory available: 57040k/65536k RAM, (5308k init code, 1080k kernel code, 484k data, 1024k dma, 600k reserved)

Hierarchical RCU implementation.

NR_IRQS:153

Configuring Blackfin Priority Driven Interrupts

console [ttyBF0] enabled, bootconsole disabled

Calibrating delay loop... 1187.84 BogoMIPS (lpj=2375680)

Mount-cache hash table entries: 512

CoreB bootstrap code to SRAM ff600000 via DMA.

Booting Core B.

Instruction Cache Enabled for CPU1

External memory: cacheable in instruction cache

L2 SRAM : uncacheable in instruction cache

Data Cache Enabled for CPU1

External memory: cacheable (write-through) in data cache

L2 SRAM : uncacheable in data cache

Brought up 2 CPUs

SMP: Total of 2 processors activated (4.09 BogoMIPS).

Blackfin Scratchpad data SRAM: 4 KB

Blackfin L1 Data A SRAM: 16 KB (16 KB free)

Blackfin L1 Data B SRAM: 16 KB (16 KB free)

Blackfin L1 Instruction SRAM: 16 KB (15 KB free)

Blackfin L2 SRAM: 128 KB (127 KB free)

NET: Registered protocol family 16

Blackfin DMA Controller

ezkit_init(): registering device resources

bio: create slab <bio-0> at 0

Switching to clocksource jiffies

NET: Registered protocol family 2

IP route cache hash table entries: 1024 (order: 0, 4096 bytes)

TCP established hash table entries: 2048 (order: 2, 16384 bytes)

TCP bind hash table entries: 2048 (order: 2, 16384 bytes)

TCP: Hash tables configured (established 2048 bind 2048)

TCP reno registered

NET: Registered protocol family 1

msgmni has been set to 111

io scheduler noop registered

io scheduler anticipatory registered (default)

bfin-uart: Blackfin serial driver

bfin-uart.0: ttyBF0 at MMIO 0xffc00400 (irq = 35) is a BFIN-UART

brd: module loaded

bfin-spi bfin-spi.0: Blackfin on-chip SPI Controller Driver, Version 1.0, regs_base@ffc00500, dma channel@16

smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>

eth0: SMC91C11xFD (rev 2) at 2c010300 IRQ 82 [nowait]

eth0: Ethernet addr: 00:e0:22:fe:ba:2a

bfin-wdt: initialized: timeout=20 sec (nowayout=0)

TCP cubic registered

NET: Registered protocol family 17

eth0: link down

IP-Config: Complete:

device=eth0, addr=10.100.4.50, mask=255.255.255.0, gw=10.100.4.174,

host=bf561-ezkit, domain=, nis-domain=(none),

bootserver=10.100.4.174, rootserver=10.100.4.174, rootpath=

Freeing unused kernel memory: 5308k freed

eth0: link up, 100Mbps, full-duplex, lpa 0x41E1

_____________________________________

a8888b. / Welcome to the uClinux distribution \

d888888b. / _ _ \

8P"YP"Y88 / | | |_| __ __ (TM) |

8|o||o|88 _____/ | | _ ____ _ _ \ \/ / |

8' .88 \ | | | | _ \| | | | \ / |

8`._.' Y8. \ | |__ | | | | | |_| | / \ |

d/ `8b. \ \____||_|_| |_|\____|/_/\_\ |

dP . Y8b. \ For embedded processors including |

d8:' " `::88b \ the Analog Devices Blackfin /

d8" 'Y88b \___________________________________/

:8P ' :888

8a. : _a88P For further information, check out:

._/"Yaa_: .| 88P| - http://blackfin.uclinux.org/

\ YP" `| 8P `. - http://docs.blackfin.uclinux.org/

/ \.___.d| .' - http://www.uclinux.org/

`--..__)8888P`._.' jgs/a:f - http://www.analog.com/blackfin

Have a lot of fun...

BusyBox v1.15.3 (2010-02-03 06:48:32 GMT) hush - the humble shell

root:/> echo enabled > /sys/class/tty/ttyBF0/power/wakeup

root:/> cat /sys/class/tty/ttyBF0/power/wakeup

enabled

root:/> echo standby > /sys/power/state

PM: Syncing filesystems ... done.

Freezing user space processes ... (elapsed 0.00 seconds) done.

Freezing remaining freezable tasks ... (elapsed 0.00 seconds) done.

Suspending console(s) (use no_console_suspend to debug)

(Type in terminal and it can not wake up)

--

Follow-ups

--- Graf Yang 2010-03-19 05:07:01

When the CoreB wakes up, we need disable its cache, so it can get the variable's

value which maybe newly assigned by CoreA, like secondary_stack...

But the dcache turn off code in _coreb_trampoline_start seems cannot disable

the dcache.

There are several workarounds,

1. Call blackfin_invalidate_entire_dcache() in platform_cpu_die().

2. Add flushinv[p0] before assign _secondary_stack to sp/usp in _coreb_start.

3. Clear bits DMC of DMEM_CONTROL in _coreb_trampoline_start.

The workaround 1 have been committed. Now it can be waked up by uart.

--- Vivi Li 2010-03-22 05:35:51

OK now.

Close it.

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