FAQ: [#6003] Traps test 43/45/47/49 fails on bf533-stamp/ezkit(2010)

[#6003] Traps test 43/45/47/49 fails on bf533-stamp/ezkit

Submitted By: Vivi Li

Open Date

2010-04-12 04:51:26

Priority:

Medium Assignee:

Sonic Zhang

Status:

Open Fixed In Release:

N/A

Found In Release:

2010R1 Release:

Category:

N/A Board:

N/A

Processor:

BF533 Silicon Revision:

Is this bug repeatable?:

Yes Resolution:

N/A

Uboot version or rev.:

Toolchain version or rev.:

toolchain.2010_Jan_22

App binary format:

N/A

Summary: Traps test 43/45/47/49 fails on bf533-stamp/ezkit

Details:

Traps test 43/45/47/49 fails on bf533-stamp and ezkit. On other platform, traps test can pass.

./traps_test -1

(...)

Running test 43 for exception 0x24: Data read misaligned address violation

... FAIL (test failed with wrong EXCAUSE, expected 24, but got 3f)

FAIL (test failed with wrong EXCAUSE, expected 0x24, but got 0x3f)

FAIL (test completed properly 0/1 times)

Running test 44 for exception 0x24: Data write misaligned address violation

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

Running test 45 for exception 0x24: Stack set to odd address - misaligned address violation

... FAIL (test failed with wrong EXCAUSE, expected 24, but got 3f)

FAIL (test failed with wrong EXCAUSE, expected 0x24, but got 0x3f)

FAIL (test completed properly 0/1 times)

Running test 46 for exception 0x24: Stack push to odd address

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

Running test 47 for exception 0x26: Data Read CPLB miss

... FAIL (test failed with wrong EXCAUSE, expected 26, but got 3f)

FAIL (test failed with wrong EXCAUSE, expected 0x26, but got 0x3f)

FAIL (test completed properly 0/1 times)

Running test 48 for exception 0x26: Data Write CPLB miss

... PASS (test completed 1/1 times, as expected by signal 7: Bus error)

Running test 49 for exception 0x26: Stack CPLB miss

... FAIL (test failed with wrong EXCAUSE, expected 26, but got 3f)

FAIL (test failed with wrong EXCAUSE, expected 0x26, but got 0x3f)

FAIL (test completed properly 0/1 times)

(...)

84/88 tests passed

Follow-ups

--- Robin Getz 2010-04-16 11:27:59

What version of silicon - there were some known differences between versions

(due to anomalies...)

-Robin

--- Vivi Li 2010-04-18 23:04:06

Silicon version is 0.3 on bf533-stamp;

Silicon version is 0.4 on bf533-ezkit.

--- Vivi Li 2010-06-30 23:33:14

Update error log:

Running test 50 for exception 0x24: Data read misaligned address violation

... FAIL (test failed with wrong EXCAUSE, expected 24, but got 3f)

FAIL (test failed with wrong EXCAUSE, expected 0x24, but got 0x3f)

FAIL (test completed properly 0/1 times)

Running test 52 for exception 0x24: Stack set to odd address - misaligned

address violation

... FAIL (test failed with wrong EXCAUSE, expected 24, but got 3f)

FAIL (test failed with wrong EXCAUSE, expected 0x24, but got 0x3f)

FAIL (test completed properly 0/1 times)

Running test 54 for exception 0x26: Data Read CPLB miss

... FAIL (test failed with wrong EXCAUSE, expected 26, but got 3f)

FAIL (test failed with wrong EXCAUSE, expected 0x26, but got 0x3f)

FAIL (test completed properly 0/1 times)

Running test 56 for exception 0x26: Stack CPLB miss^M

... FAIL (test failed with wrong EXCAUSE, expected 26, but got 3f)

FAIL (test failed with wrong EXCAUSE, expected 0x26, but got 0x3f)

FAIL (test completed properly 0/1 times)

--- Sonic Zhang 2010-07-13 06:07:17

Hardware Error interrupt for "External Memory Address Error" is

triggered ahead of data misaligned exception(0x24) and data access CPLB miss

exception(0x26) on bf533 if:

1) read from an odd address outside real memory region.

2) rts to an odd address outside real memory region.

Walkaround by use POPULATED_EVEN and POPULATED_ODD in real memory (<32M) for

tests against except 0x24.

Because CPLB entry can't be easily invalidated from user space, tests agait

exception 0x26 has no walkaround for bf533. Just don't run these tests on

bf533.

--- Robin Getz 2010-07-21 11:17:42

Exceptions (EVT3) should always be triggered before hardware errors (EVT5)

according to the manual.

"Exceptions are synchronous to the instruction stream. In other words, a

particular instruction causes an exception when it attempts to finish

execution. No instructions after the offending instruction are executed before

the exception handler takes effect."

If you are correct - it sounds like a new anomaly. Can you check with

processor.support?

Thanks

-Robin

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