[#6190] BF561-EZKIT SMP kernel can not wake up by uart
Submitted By: Vivi Li
Open Date
2010-08-17 05:58:11 Close Date
2010-11-09 02:23:27
Priority:
Medium Assignee:
steven miao
Status:
Closed Fixed In Release:
N/A
Found In Release:
2010R1 Release:
Category:
N/A Board:
EZKIT Lite
Processor:
BF561 Silicon Revision:
Is this bug repeatable?:
Yes Resolution:
Fixed
Uboot version or rev.:
Toolchain version or rev.:
gcc4.3-2010_Aug_04
App binary format:
Summary: BF561-EZKIT SMP kernel can not wake up by uart
Details:
BF561-EZKIT SMP kernel can not wake up by uart in latest trunk.
Last passed verstion:
--
kernel: Linux release 2.6.34.2-ADI-2010R1-pre-svn9048, build #56 SMP Thu Aug 5 05:06:59 GMT 2010
toolchain: bfin-uclinux-gcc release gcc version 4.3.4 (ADI-trunk/svn-3951)
user-dist: release svn-9772, build #789 Thu Aug 5 05:05:34 GMT 2010
First failed version:
kernel: Linux release 2.6.34.2-ADI-2010R1-pre-svn9057, build #60 SMP Fri Aug 6 06:49:43 GMT 2010
user-dist: release svn-9774, build #835 Fri Aug 6 06:48:26 GMT 2010
Bellow is the log:
Linux version 2.6.34.4-ADI-2010R1-pre-svn9082 (test@uclinux65-561-SMP) (gcc version 4.3.5 (ADI-trunk/svn-4747) ) #28 SMP Mon Aug0
register early platform devices
bootconsole [early_shadow0] enabled
bootconsole [early_BFuart0] enabled
early printk enabled on early_BFuart0
Board Memory: 64MB
Kernel Managed Memory: 64MB
Memory map:
fixedcode = 0x00000400-0x00000490
text = 0x00001000-0x00116298
rodata = 0x001162a0-0x0016c82c
bss = 0x0016d000-0x0017eec0
data = 0x0017eec0-0x00190000
stack = 0x0018e000-0x00190000
init = 0x00190000-0x00700000
available = 0x00700000-0x03f00000
DMA Zone = 0x03f00000-0x04000000
Hardware Trace Active and Enabled
Boot Mode: 0
Reset caused by Software reset
Blackfin support (C) 2004-2010 Analog Devices, Inc.
Compiled for ADSP-BF561 Rev 0.5
Blackfin Linux support by http://blackfin.uclinux.org/
Processor Speed: 600 MHz core clock and 100 MHz System Clock
NOMPU: setting up cplb tables
Instruction Cache Enabled for CPU0
External memory: cacheable in instruction cache
L2 SRAM : uncacheable in instruction cache
Data Cache Enabled for CPU0
External memory: cacheable (write-through) in data cache
L2 SRAM : uncacheable in data cache
PERCPU: Embedded 6 pages/cpu @00785000 s3776 r8192 d12608 u65536
pcpu-alloc: s3776 r8192 d12608 u65536 alloc=16*4096
pcpu-alloc: [0] 0 [0] 1
Built 1 zonelists in Zone order, mobility grouping off. Total pages: 16002
Kernel command line: root=/dev/mtdblock0 rw clkin_hz=30000000 earlyprintk=serial,uart0,57600 console=ttyBF0,57600 ip=10.100.4.50f
PID hash table entries: 256 (order: -2, 1024 bytes)
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory available: 56716k/65536k RAM, (5568k init code, 1108k kernel code, 488k data, 1024k dma, 632k reserved)
Hierarchical RCU implementation.
NR_IRQS:153
Configuring Blackfin Priority Driven Interrupts
console [ttyBF0] enabled, bootconsole disabled
Calibrating delay loop... 1187.84 BogoMIPS (lpj=2375680)
Mount-cache hash table entries: 512
CoreB bootstrap code to SRAM ff600000 via DMA.
Booting Core B.
Instruction Cache Enabled for CPU1
Data Cache Enabled for CPU1
Brought up 2 CPUs
SMP: Total of 2 processors activated (4.09 BogoMIPS).
Blackfin Scratchpad data SRAM: 4 KB
Blackfin L1 Data A SRAM: 16 KB (16 KB free)
Blackfin L1 Data B SRAM: 16 KB (16 KB free)
Blackfin L1 Instruction SRAM: 16 KB (15 KB free)
Blackfin L2 SRAM: 128 KB (127 KB free)
NET: Registered protocol family 16
Blackfin DMA Controller
ezkit_init(): registering device resources
bio: create slab <bio-0> at 0
bfin-spi bfin-spi.0: Blackfin on-chip SPI Controller Driver, Version 1.0, regs_base@ffc00500, dma channel@16
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 2048 (order: 2, 16384 bytes)
TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP reno registered
UDP hash table entries: 128 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 128 (order: 0, 4096 bytes)
NET: Registered protocol family 1
msgmni has been set to 110
io scheduler noop registered (default)
bfin-uart: Blackfin serial driver
bfin-uart.0: ttyBF0 at MMIO 0xffc00400 (irq = 35) is a BFIN-UART
brd: module loaded
smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@fluxnic.net>
eth0: SMC91C11xFD (rev 2) at 2c010300 IRQ 82 [nowait]
eth0: Ethernet addr: 00:e0:22:fe:ba:2a
bfin-wdt: initialized: timeout=20 sec (nowayout=0)
TCP cubic registered
NET: Registered protocol family 17
eth0: link down
IP-Config: Complete:
device=eth0, addr=10.100.4.50, mask=255.255.255.0, gw=10.100.4.174,
host=bf561-ezkit, domain=, nis-domain=(none),
bootserver=10.100.4.174, rootserver=10.100.4.174, rootpath=
Freeing unused kernel memory: 5568k freed
eth0: link up, 100Mbps, full-duplex, lpa 0x41E1
_____________________________________
a8888b. / Welcome to the uClinux distribution \
d888888b. / _ _ \
8P"YP"Y88 / | | |_| __ __ (TM) |
8|o||o|88 _____/ | | _ ____ _ _ \ \/ / |
8' .88 \ | | | | _ \| | | | \ / |
8`._.' Y8. \ | |__ | | | | | |_| | / \ |
d/ `8b. \ \____||_|_| |_|\____|/_/\_\ |
dP . Y8b. \ For embedded processors including |
d8:' " `::88b \ the Analog Devices Blackfin /
d8" 'Y88b \___________________________________/
:8P ' :888
8a. : _a88P For further information, check out:
._/"Yaa_: .| 88P| - http://blackfin.uclinux.org/
\ YP" `| 8P `. - http://docs.blackfin.uclinux.org/
/ \.___.d| .' - http://www.uclinux.org/
`--..__)8888P`._.' jgs/a:f - http://www.analog.com/blackfin
Have a lot of fun...
BusyBox v1.16.2 (2010-08-16 04:44:10 GMT) hush - the humble shell
root:/> echo enabled > /sys/class/tty/ttyBF0/power/wakeup
root:/> cat /sys/class/tty/ttyBF0/power/wakeup
enabled
root:/> echo standby > /sys/power/state
PM: Syncing filesystems ... done.
Freezing user space processes ... (elapsed 0.01 seconds) done.
Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.
Suspending console(s) (use no_console_suspend to debug)
U-Boot 2010.06-svn2356 (ADI-2010R1-pre) (Jul 19 2010 - 10:38:17)
CPU: ADSP bf561-0.3 (Detected Rev: 0.5) (bypass boot)
Board: ADI BF561 EZ-Kit Lite board
Support: http://blackfin.uclinux.org/
Clock: VCO: 600 MHz, Core: 600 MHz, System: 100 MHz
RAM: 64 MiB
Flash: 8 MiB
In: serial
Out: serial
Err: serial
KGDB: [on serial] ready
Net: SMC91111-0
Hit any key to stop autoboot: 0
bfin>
Follow-ups
--- steven miao 2010-09-03 06:07:04
Add offset to avoid .l1.text section relocation overwrite coreb start
entry. After coreb wakeup by IPI, it will execute coreb_trampoline_start
entry at coreb l1 code area, but l1 iflush patch for ANOMALY_05000491
overwrite the coreb_trampoline_start code area, so wakeup fail.
--- Michael Hennerich 2010-09-03 11:18:00
the change needs fixing
--- steven miao 2010-09-10 06:11:16
link coreb_trampoline_start to .l1.text section instead of add offset 0x200
to relocate l1 mem.
--- Vivi Li 2010-11-09 02:23:27
OK, close it.
Files
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Duplicates
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Tags
File Name File Type File Size Posted By
config.linux.uart_wakeup application/octet-stream 30255 Vivi Li