[#7232] SMP bf561-ezkit kernel crash in change_cpufreq test
Submitted By: Vivi Li
Open Date
2012-08-09 03:10:24 Close Date
2012-08-23 04:18:31
Priority:
Medium Assignee:
steven miao
Status:
Closed Fixed In Release:
N/A
Found In Release:
N/A Release:
Category:
N/A Board:
N/A
Processor:
BF561 Silicon Revision:
Is this bug repeatable?:
Yes Resolution:
Fixed
Uboot version or rev.:
Toolchain version or rev.:
gcc4.3-2012_Feb_15
App binary format:
N/A
Summary: SMP bf561-ezkit kernel crash in change_cpufreq test
Details:
SMP bf561-ezkit kernel crash in change_cpufreq test after kernel upgrade to 3.5.0.
--
Linux version 3.5.0-ADI-2012R1-pre-00806-g8528770 (test@uclinux65-561-SMP) (gcc version 4.3.5 (ADI-trunk/svn-5764) ) #24 SMP Wed2
register early platform devices
bootconsole [early_shadow0] enabled
bootconsole [early_BFuart0] enabled
early printk enabled on early_BFuart0
Board Memory: 64MB
Kernel Managed Memory: 64MB
Memory map:
fixedcode = 0x00000400-0x00000490
text = 0x00001000-0x00150b78
rodata = 0x00150b80-0x00196e4c
bss = 0x00197000-0x001a8e44
data = 0x001a8e60-0x001be000
stack = 0x001bc000-0x001be000
init = 0x001be000-0x0077b000
available = 0x0077b000-0x03f00000
DMA Zone = 0x03f00000-0x04000000
Hardware Trace active and enabled
Boot Mode: 0
Blackfin support (C) 2004-2010 Analog Devices, Inc.
Compiled for ADSP-BF561 Rev 0.5
Blackfin Linux support by http://blackfin.uclinux.org/
Processor Speed: 600 MHz core clock and 100 MHz System Clock
NOMPU: setting up cplb tables
NOMPU: setting up cplb tables
Instruction Cache Enabled for CPU0
External memory: cacheable in instruction cache
L2 SRAM : uncacheable in instruction cache
Data Cache Enabled for CPU0
External memory: cacheable (write-through) in data cache
L2 SRAM : uncacheable in data cache
PERCPU: Embedded 7 pages/cpu @00800000 s5504 r8192 d14976 u32768
Built 1 zonelists in Zone order, mobility grouping off. Total pages: 16002
Kernel command line: root=/dev/mtdblock0 rw clkin_hz=30000000 earlyprintk=serial,uart0,57600 console=ttyBF0,57600 ip=10.100.4.50f
PID hash table entries: 256 (order: -2, 1024 bytes)
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory available: 56212k/65536k RAM, (5876k init code, 1342k kernel code, 438k data, 1024k dma, 644k reserved)
Hierarchical RCU implementation.
NR_IRQS:153
Configuring Blackfin Priority Driven Interrupts
start_kernel(): bug: interrupts were enabled early
console [ttyBF0] enabled, bootconsole disabled
console [ttyBF0] enabled, bootconsole disabled
Calibrating delay loop... 1185.79 BogoMIPS (lpj=2371584)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
Booting Core B.
Brought up 2 CPUs
Instruction Cache Enabled for CPU1
External memory: cacheable in instruction cache
L2 SRAM : uncacheable in instruction cache
Data Cache Enabled for CPU1
External memory: cacheable (write-through) in data cache
L2 SRAM : uncacheable in data cache
SMP: Total of 2 processors activated (2371.58 BogoMIPS).
Blackfin Scratchpad data SRAM: 4 KB
Blackfin Scratchpad data SRAM: 4 KB
Blackfin L1 Data A SRAM: 16 KB (16 KB free)
Blackfin L1 Data A SRAM: 16 KB (16 KB free)
Blackfin L1 Data B SRAM: 16 KB (16 KB free)
Blackfin L1 Data B SRAM: 16 KB (16 KB free)
Blackfin L1 Instruction SRAM: 16 KB (15 KB free)
Blackfin L1 Instruction SRAM: 16 KB (15 KB free)
Blackfin L2 SRAM: 128 KB (127 KB free)
NET: Registered protocol family 16
Blackfin DMA Controller
ezkit_init(): registering device resources
bio: create slab <bio-0> at 0
bfin-spi bfin-spi.0: master is unqueued, this is deprecated
bfin-spi bfin-spi.0: Blackfin on-chip SPI Controller Driver, Version 1.0, regs@ffc00500, dma channel@16
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 2048 (order: 2, 16384 bytes)
TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP: reno registered
UDP hash table entries: 256 (order: 1, 8192 bytes)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
NET: Registered protocol family 1
debug-mmrs: setting up Blackfin MMR debugfs
------------[ cut here ]------------
WARNING: at kernel/smp.c:461
Modules linked in:
ADSP-BF561-0.5 600(MHz CCLK) 100(MHz SCLK) (mpu off)
Linux version 3.5.0-ADI-2012R1-pre-00806-g8528770 (test@uclinux65-561-SMP) (gcc version 4.3.5 (ADI-trunk/svn-5764) ) #24 SMP Wed2
SEQUENCER STATUS: Not tainted
SEQSTAT: 0000c021 IPEND: 8008 IMASK: 003f SYSCFG: 0006
Peripheral interrupts masked off
Kernel interrupts masked off
EXCAUSE : 0x21
Double Fault
Kernel OOPS in progress
Deferred Exception context
CURRENT PROCESS:
COMM=swapper/0 PID=1 CPU=1
invalid mm
return address: [0x00043812]; contents of:
0x000437f0: 1ff2 0c06 1ffa 9a21 2ff9 0000 04c3 e14c
0x00043800: 0000 014f e10c 0000 3018 3239 3402 0c44
0x00043810: 1003 [0001] 2000 e14a 0000 e10a 0000 9153
0x00043820: 6002 304b 5211 0e08 180a 4e08 5010 3208
ADSP-BF561-0.5 600(MHz CCLK) 100(MHz SCLK) (mpu off)
Linux version 3.5.0-ADI-2012R1-pre-00806-g8528770 (test@uclinux65-561-SMP) (gcc version 4.3.5 (ADI-trunk/svn-5764) ) #24 SMP Wed2
SEQUENCER STATUS: Not tainted
SEQSTAT: 00060021 IPEND: 8028 IMASK: 003f SYSCFG: 0006
Peripheral interrupts masked off
Kernel interrupts masked off
EXCAUSE : 0x21
--
Follow-ups
--- steven miao 2012-08-16 02:25:38
shoud not disable irq in cpufreq
--- Mingquan Pan 2012-08-23 05:16:57
Yes, fixed.
Files
Changes
Commits
Dependencies
Duplicates
Associations
Tags
File Name File Type File Size Posted By
config.config.change_cpufreq application/octet-stream 52077 Vivi Li
config.linux.change_cpufreq application/octet-stream 32360 Vivi Li