I found a bug of the Blackfin boot ROM. The ADSP-BF533 doesn't toggle the HWAIT in the slave mode. Let me inform if this is the known issue. I want to know the detail of this bug. Following is silicon bug, but I reported it here to share the info with the GNU tool chain users.
- ADSP-BF533 rev 0.5 silicon
- bfin-elf-ldr 2014R1-RC2
- Workaround : Add "ignore header" at the top of LDR file.
If you generate the LDR by bfin-elf-ldr for SPI slave mode like :
bfin-elf-ldr -T BF533 -c -g 1 jsp.ldr jsp --bmode spi
the ADSP-BF533 doesn't toggle HWAIT. It doen't depend on the PF pin. ( I checked with PF1 and PF13 ). But the generated LDR is completely healthy. I checked it with EE-240, but could not find any bad point in the LDR file.
To solve it, you just have to add the following dummy data at the beginning of LDR file by hand.
0x00 0x00 0x80 0xff // loading dummy address
0x04 0x00 0x00 0x00 // length (4)
0x32 0x00 // PF1+RESVECT(BF533)+IGNORE
0xDE 0xAD 0xBE 0xEF // dummy data
Because this is "ignore" block, the header and data are just ignored by boot ROM, but HWAIT toggle.
This problem is not observed if you generate LDR by VDSP elfloader, because the elfloader always add above dummy block for multi DXE boot while you have only one boot DXE.
This issue is not recorded in the silicon anomaly. But if it is known issue, please let me know where I can see the detail .
I got answer. This is not the bug of ROM code, but the problem of documentation.
The BF533 firmeware ( ver3 ) source code cleary says in comment if the ignore flat is checked, it setup the PF flag for HWAIT. This is the only point where the PF is set up.
But EE-240 doesn't declare it. Alternatively, EE-240 clealy says VDSP uses the IGNORE block only for the multi-DXE boot. This is not collect according to the VDSP elfloader DXE.
so, the conclusion is :