Why do I get scan failures when trying to connect using the higher JTAG/SWD frequencies on my In-Circuit Emulator?
There is a relationship between the JTAG frequency and the core clock frequency on the target processor. The core clock should be at least twice the JTAG frequency in order for the JTAG interface to operate properly. On newer processors, the core clock can be configured in your application.
With ADSP-BF70x processors, a similar relationship exists between the JTAG/SWD frequency and the system clock. Again, the system clock should be at least twice the JTAG/SWD frequency, and this clock can be configured in your application.
If the JTAG/SWD and core/system clock relation is not followed, scan failures may prevent the emulator from connecting to the processor.