Unable to connect to the target processor via JTAG in or after Sleep mode

I have a program which runs from flash and places the processor on my Blackfin target in Sleep mode. While the processor is in Sleep mode, I could not connect via JTAG. Is this the expected behaviour? How can I re-establish the connection?

  • 0
    •  Analog Employees 
    on May 8, 2009 2:54 PM

    CraigG wrote:

    I have a program which runs from flash and places the processor on my Blackfin target in Sleep mode. While the processor is in Sleep mode, I could not connect via JTAG. Is this the expected behaviour? How can I re-establish the connection?

    When the processor is in Sleep or Deep Sleep mode, the JTAG is inaccessible, so you will not be able to connect to your target.

    This is because the CCLK is disabled after STOPCK is set (by placing the processor in Sleep or Deep Sleep). Without an active CCLK, the JTAG cannot function and the only way to clear it is by a wake-up event. In other words, you cannot have software clear the STOPCK bit because there is no core clock available to allow that code to execute. The STOPCK bit is cleared by the hardware when an enabled SIC_IWR event takes place. One way to achieve this would be to use the EMU~ pin tied to a wake-up event. You could connect the EMU~ pin to one of the programmable flags, and set the corresponding interrupt on the PF as a wake-up from Sleep into either 'Active' or 'Full On', so that a JTAG connection can be established.

    Please also see the section "Operating Mode Transitions" in the Processor Reference Manual for your target as this details the changes that take place when switching between operating modes. This can be found under the 'Dynamic Power Management' section.

  • 0
    •  Analog Employees 
    on Apr 29, 2019 10:45 AM
    This question has been closed by the EZ team and is assumed answered.