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Issues on EV-21569-som Schematic

Thread Summary

The user inquired about the EV-21569-SOM board schematic, specifically the PG1 and PG2 labels for the +1.35V and VDD_INT regulators, the correct voltage for VDD_EXT, and the VTT voltage for DDR3. The final answer confirmed that PG1 and PG2 are connected to the power good signals of the previous buck converters, VDD_EXT is 3.3V (schematic uses 3V symbols), and VTT is 0.675V, which is half of VDDQ (1.35V).
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Category: Datasheet/Specs
Product Number: ADSP-21569

I have several questions regarding the schematic for the ev-21569-som board.

1. On the power supply page (11 of 12), the voltage regulators for +1.35 and _1.0 have
the enable inputs marked driven by labels PG1 and PG2. However, I cannot find
any reference to these labels anywhere else in the schematic. What are these
labels supposed to be connected to?

2. The data sheet for the ADSP-21569 shows that VDD_EXT is 3.3v "nominal" and
the minimum voltage is 3.13v. However, throughout the schematic the voltages
shown are 3.0v, not 3.3, except for a single instance where the schematic shows
3.3v at VIN on U9 (the TPS51200 Sink/Source DDR regulator). Please confirm
that: (a) the schematic is incorrect and VDD_EXT is supposed to be 3.3V, not
3.0V as shown throughout the schematic; and (b) the resistors setting the
voltage output on U18 (LT8609) are correct values for 3.3V, not 3.0V (see
R87, R82, R79).

3. I want to confirm that VTT in the circuit for the DDR3 is .75v.

Thread Notes

  • Hello,

    Please find the details for your queries here. 

    Regarding the first question The voltage regulators for +1.35V and VDD_INT have their enable inputs connected to the power good(PG) signal pin of the previous buck converter IC,  please check the below image

    Regarding the second question, yes the nominal voltage for VDD_EXT is indeed 3.3V, as specified in the ADSP-21569 datasheet.

    Additionally, we have reached out to our internal team regarding the schematic label, and we will update you as soon as we receive the response from them

    Regarding the third question, According to the TPS51200 datasheet, the termination voltage (VTT) is typically half of the DDR supply voltage (VDDQ) please check the below image . Since our VDDQ is 1.35V, We confirm that the VTT in the circuit for the DDR3 is 0.675V.

    The termination voltage measured on the board is 0.675v. We have confirmed this using a DSO (Digital Storage Oscilloscope), and We will attach the probe image for your reference,

     Hope this helps.

    Regards,

    Santhakumari.V

  • Hi,

    Regarding Q2, Our HW designer confirmed that VDD_EXT is 3.3V, but that tool used to design the board uses 3V symbols instead of 3.3V. Up until recently the standard to represent 3.3V was actually just 3V. Now that standards have changed and symbols are more specific.

    Hope this helps.

    Best Regards,
    Santhakumari.V