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Receiver SPORT interrupt not observed

Category: Software
Product Number: SC594 ARM
Software Version: CCES 2.10.1

I am using SC594 processor in a custom platform. I am trying to run ADC-DAC pass through code in ARM. We are using PCG to generate clock for ADC, A2B, and SPORTS.

>>When the Clock is probed it is observed as expected

We are using SPORT 4A to receive data from ADC. We have configured DMA in Descriptor mode. I have taken these configurations in reference to the example given in BSP  of SC59x.

(Reference: C:\Analog Devices\EV-SC59x_EZ-KIT-Rel2.0.0\EV-SC59x_EZ-KIT\Examples\drivers\adc\Audio_Talkthrough_I2S\EV-SOMCRR-EZKIT\SC594\arm\AD_Talkthrough_I2S_SC594_Cortex_Core0)

Note:  I am using TDM instead of I2S

I have configured SPU Registers for SPORT 4A and configured the SPORT to receive a callback when XCOUNT reaches zero.

When I keep the breakpoint in callback function and run, the breakpoint never hits(Not getting receiver SPORT interrupt)

When I check the SPORT registers I am seeing as below

Bits FSERRSTAT, FSERRMSK, DERRSMSK, DERRPMSK are set in SPORT4_ERR_A register.

Can You Please guide me on what would have gone wrong here?

  • Hi,

    The SPORT_ERR_A.FSERRSTAT bit indicates that the half SPORT has detected a frame sync when the bit count (bits remaining in the frame) is non-zero. When a half SPORT is receiving or transmitting, its bit count is set to a word length (for example,SPORT_CTL_B.SLEN = 31). After each serial clock edge, the half SPORT decrements the transfer's bit count. After the word is received or transmitted, the transfer's bit count reaches zero, and the half SPORT resets it (for example, to 32) on next frame sync. Normal SPORT data transfers always have a non-zero bit count value when active transmission or reception is occurring. Normal SPORT frame syncs occur after the bit count becomes zero. We suspect that this might be the cause of the issue so, can you check your frame sync configuration in your project.

    FSERRMSK, DERRSMSK, DERRPMSK when these bits are set it will unmasks (enables) the half SPORT to generate the error interrupt request according to the error occurred, these bits will sets automatically inside the driver and it is expected.

    For more information about FSERRSTAT bit please refer topic "Error Detection (Status) Interrupt" in SC 594 Hardware reference manual.

    Hope it helps

    Regards,
    Santhakumari.K