FAQ: How do I instruct the compiler to generate SIMD code? It is not generated by default.

Question:

How do I instruct the compiler to generate SIMD code? It is not generated by default.

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Answer:

SIMD code is not generated by default for most SHARC processors for reasons that are explained below. The compiler supports a number of switches that allow you to control when SIMD code is generated. These switches are:

  • -loop-simd
    • Enables automatic use of SIMD mode in loops, aggregate assignments and inlined memcpy operations by asserting that data buffers are safe to access in this mode.
  • -asms-safe-in-simd-for-loops
    • Instructs the compiler that inline asm() statements inside loops marked with the SIMD_for pragma are safe to run unchanged in SIMD mode.
  • -linear-simd
    • Instructs the compiler to look for opportunities to use SIMD mode for parallel computations in linear code.
  • -no-linear-simd
    • Instructs the compiler not to use SIMD mode for parallel computations in linear code.
  • -no-simd
    • Disables all automatic use of SIMD mode.

 

On some SHARC processors, SIMD memory accesses to external memory are not possible, or may only be possible for certain memory types. Attempting to perform SIMD accesses to external memory on these processors can result in issues at run-time as data accesses using the 2nd processing element (“PEy”) will have no effect. In CrossCore Embedded Studio, the compiler’s behavior is conservative and it will not generate SIMD code if there is the possibility that SIMD accesses may fail. This restriction affects the following processors, for which SIMD code will not be generated by default:

  • ADSP-21160          // SIMD accesses to external memory may be affected by hardware anomalies
  • ADSP-21161          // SIMD accesses to external memory are not supported
  • ADSP-21367/8/9    // SIMD accesses to external memory are not supported
  • ADSP-21371/5       // SIMD accesses to external memory are not supported
  • ADSP-214xx          // SIMD accesses to external memory via the AMI bus are not supported

For the following processors, SIMD code is generated by default. These processors do not support direct access of external memory, so the limitations described above do not apply.

  • ADSP-2126x
  • ADSP-21363/4/5/6

Documentation

For more information on SIMD code generation, see the section “SIMD Support” in the C/C++ Compiler Manual.

Differences from VisualDSP++

In VisualDSP++, the compiler’s default behavior was to generate SIMD code, as long as certain criteria concerning alignment, aliasing and performance gains were met. If an application performed SIMD accesses, and the application used external memory, there was the potential for run-time errors that were difficult to diagnose. As described above, the compiler’s behavior in CrossCore Embedded Studio is now more conservative, which may result in out-of-the-box compiler performance appearing to be poorer. The switch “-loop-simd” can be used to reinstate the behavior of the VisualDSP++ compiler.


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