Analog.com Analog Dialogue Wiki English 简体中文
EngineerZone
EngineerZone
  • Log In
  • Site
  • Search
  • User
  • Support

    Popular Forums

    • RF and Microwave
    • Power Management
    • Video
    • FPGA Reference Designs
    • Precision ADCs
    • Linux Software Drivers
    • SigmaDSP Processors & SigmaStudio Dev. Tool

    Product Forums

    • A2B
    • Amplifiers
    • Analog Microcontrollers
    • Clock and Timing
    • Data Converters
    • Direct Digital Synthesis (DDS)
    • Energy Monitoring and Metering
    • Interface and Isolation
    • MEMS Inertial Sensors
    • Processors and DSP
    • Switches/Multiplexers
    • Temperature Sensors
    • Voltage References
    View All

    Application Forums

    • Audio
    • Automated Test Equipment (ATE)
    • Condition-Based Monitoring
    • Depth, Perception & Ranging Technologies
    • Embedded Vision Sensing Library
    • Motor Control Hardware Platforms
    • Optical Sensing
    • Precision Technology Signal Chains Library
    • Video
    • Wireless Sensor Networks Reference Library

    Design Center Forums

    • ACE Evaluation Software
    • ADEF System Platforms
    • Design Tools and Calculators
    • FPGA Reference Designs
    • Linux Software Drivers
    • Microcontroller no-OS Drivers
    • Reference Designs
    • Signal Chain Power (SCP)
    • Software Interface Tools
    • System Demonstration Platform (SDP) Support
  • Learn

    Highlighted Webinar

    How ADI is keeping up with security threats in retail, logistics and banking point of sale (POS) systems

    Recent Discussions

    • Csharp bindings for libm2k and calibrateFromContext function
    • ADALM-PLUTO maximum frequency
    • Issue running built programs on Pluto
    • Activity: Simple Op Amps, For ADALM1000 Fig. 1.3 Buffering example
    • ADALM-PLUTO [NETWORK] vs [USB_ETHERNET]

    Places

    • ADI Education Home
    • ADI Education China
    • ADI Education India
    • ADI Education Philippines
    • StudentZone (Analog Dialogue)
    • Virtual Classroom

    Latest Webinars

    • How ADI is keeping up with security threats in retail, logistics and banking point of sale (POS) systems
    • Improving System Precision with DACs
    • Multidimensional Simulations of Beamformers and other RF Integrated Circuits in Keysight SystemVue
    • Improve Smart Building Energy Efficiency with Industrial Ethernet Controlled Air Conditioning (HVAC) Systems
    • Sustainable Motion Control Solutions for High Performance Servo Drives
    View All Webinars
  • Community Hub

    Challenge Yourself!

      KCC's Quizzes: AQQ 236 about strange marking on airplane engines
    View All

    Places

    • Community Help
    • Logic Lounge

    Resources

    • EZ Code of Conduct
    • Getting Started Guide
    • ADI: Words Matter
    • Community Help Videos
    View All
  • Blogs

    Highlighted Blogs

    Why You Want to Authenticate Everything

     

    Can LTspice Break Physics?

    Latest Blogs

    • Crawl, Walk, And Run - The Journey To Create The Phaser
    • Hardware Holds The Key To Making Industrial Systems IEC 62443 Compliant
    • Behind the Scenes of DIYRadio Blogs: An Introduction
    • Empowering Surveillance Cameras To Capture A Scene Without Being Heard
    • Mastering The Metrics Makes Specifying Encoders Simpler
    Read All Blogs

    ADI Blogs

    • EZ Spotlight
    • The Engineering Mind
  • Partners

    Electronic Design Services - PartnerZone

    • Boston Engineering
    • Calian, Advanced Technologies
    • Colorado Engineering Inc. (DBA CAES AT&E)
    • Clockworks Signal Processing
    • Epiq Solutions
    • Fidus
    • PalmSens
    • Richardson RFPD
    • Tri-Star Design, Inc.
    • VadaTech
    • Vanteon
    • X-Microwave
    View All
CrossCore Embedded Studio and Add-ins
  • Processors and DSP
  • Software and Development Tools
  • CrossCore Embedded Studio and Add-ins
  • Cancel
CrossCore Embedded Studio and Add-ins
Documents FAQ: How do I instruct the compiler to generate SIMD code? It is not generated by default.
  • Blogs
  • Q&A
  • Docs/FAQs
  • Members
  • Tags
  • More
  • Cancel
  • FAQ
  • +a.b silicon into a x.y silicon target: FAQ
  • +accel_xxxx: FAQ
  • +ADC & DAC in audio application: FAQ
  • +Add version of application in loader file: FAQ
  • +Add-in license: FAQ
  • +ADI_SPI_TRANSCEIVER: FAQ
  • +adi_spu_Init() API: FAQ
  • +ADSO-BF609 EZkit: FAQ
  • +ADSP-21364: FAQ
  • +ADSP-214xx: FAQ
  • +ADSP-21569 Ez-kit: FAQ
  • +ADSP-21569: FAQ
  • +ADSP-BF609 EZKIT: FAQ
  • +ADSP-BF609: FAQ
  • +ADSP-BF707: FAQ
  • +ADSP-BF70x: FAQ
  • +ADSP-SC589: FAQ
  • +ADSP-SC58x: FAQ
  • +ADSP-SC598: FAQ
  • +ADSP-SC5xx: FAQ
  • +ADSP21489: FAQ
  • +ADSP215xx: FAQ
  • +alignment pragma: FAQ
  • +ARM CORE: FAQ
  • +ARM to Sharc: FAQ
  • +avoid when a project is getting build: FAQ
  • +BF-609 Evaluation board: FAQ
  • +BF518 Processor: FAQ
  • +BF703: FAQ
  • +BF706 EZ-KIT: FAQ
  • +BF706: FAQ
  • +BF706mini BSP project: FAQ
  • +BF707 SPI: FAQ
  • +C source file: FAQ
  • +C++ code: FAQ
  • +C-code ISRs: FAQ
  • +Callback function: FAQ
  • +Calling Library Functions: FAQ
  • +cc1138: FAQ
  • +CCES: FAQ's
  • +cldp: FAQ
  • +CLKIN: FAQ
  • +Code folding in CCES: FAQ
  • +Configuring the Loader, Linker and Archiver: FAQ
  • +connect to the Blackfin: FAQ
  • +CrossCore Embedded Studio STDIO: FAQ
  • +CROSSCORE: FAQ
  • +Data Member Alignment: FAQ
  • +Device Driver programming: FAQ
  • +Difference between Emulator and Simulator: FAQ
  • +disable prelinker: FAQ
  • +Embedded applications: FAQ
  • +EV-21569-SOM: FAQ
  • +EXTCLK_MODE: FAQ
  • +How to access stereo channels individually in the Audio_Passthrough_I2S example present in GUL BSP?
  • +How to avoid CORE0 and DEBUG: FAQ
  • +How to build a specific code from single source file for a specific core?
  • +How to convert long double into string: FAQ
  • +how to deassert Slave: FAQ
  • +How to do profiling: FAQ
  • +How to protect shared code/ data: FAQ
  • +How to resolve audio distortion issue: FAQ
  • +HW Accelerator and SW libraries: FAQ
  • +Interrupt Vector Table: FAQ
  • +LDF from C code: FAQ
  • +linker map file: FAQ
  • +List of Processors: FAQ
  • +Loader File: FAQ
  • +MCAPI package: FAQ
  • +node-locked license: FAQ
  • +non-blocking peek functions: FAQ
  • Optimization in ARM
  • +Optimizer in C/C++ compiler: FAQ
  • +PART_SPECIFIC_HEADERS: FAQ
  • +path variables: FAQ
  • +peripheral Error: FAQ
  • +PINT modules: FAQ
  • +PM bus: FAQ
  • +Project Explorer tree: FAQ
  • +PWM mode: FAQ
  • +quad SPI mode: FAQ
  • +RTOS for older Blackfin or older SHARC: FAQ
  • +SC-573 EZkit: FAQ
  • +SDRAM: FAQ
  • +SHARC 21469: FAQ
  • +SHARC0: FAQ
  • +SHARC: FAQ
  • +sharing global data between cores: FAQ
  • +SigmaStudioForSHARC: FAQ
  • -SIMD code: FAQ
    • FAQ: How do I instruct the compiler to generate SIMD code? It is not generated by default.
  • +SIMD: FAQ
  • +SPI core mode with callback: FAQ
  • +SPI flash: FAQ
  • +SPORT API: FAQ
  • +SPORT: FAQ
  • +SRCU bit: FAQ
  • +SSLDD 2.0 and SSLDD 3.0: FAQ
  • +SSLDD 3.0: FAQ
  • +SSLDD3.0: FAQ
  • +stack overflow: FAQ
  • +Static library & IP protection: FAQ
  • +suppress assembler preprocessor warning: FAQ
  • +system.svc: FAQ
  • +two PINT modules: FAQ
  • +TX and RX DMA Interrupts: FAQ
  • +U-Law and A-Law: FAQ
  • +UART Device Driver: FAQ
  • +UART ISR Callback: FAQ
  • +VisualDSP++: FAQ
  • +Wakeup processor from Hibernate: FAQ
  • +When callback occurs: FAQ
  • +word addressable program: FAQ
  • [FAQ] : Custom debug configurations in CCES
  • [FAQ] : Difference between ADZS-HPUSB and ADZS-USB ICE
  • [FAQ] : Does CCES have any API that can be used to build automation test platform with Python
  • [FAQ] : Does ICE-1000 supported ADSP-CM407F?
  • +[FAQ] : Driver example for Timer windowed watchdog period mode.
  • [FAQ] : Example code for SPORT slave trigger in ADSP-21569 Ezkit
  • [FAQ] : GUL-XP board with EZkit license
  • +[FAQ] : How to access darkmode appearance in CCES?
  • [FAQ] : How to obtain PCB library files for ADI processors
  • [FAQ] : How to pass arguments from command line in CCES runner
  • [FAQ] : How to use Device programmer in EVAL-ADICUP360 board
  • [FAQ] : Interrupt header files along with -char-size-32 switch in Sharc
  • [FAQ] : Is it possible to perform stepping into the code in CCES Runner.
  • [FAQ] : Is there a way to list symbols from library (*.dlb) file?
  • [FAQ] : Is there a way to mangle or remove internal symbols ?
  • [FAQ] : sizeof() built-in function in BF and Sharc processors
  • [FAQ] : Streaming Data input and output in CCES
  • [FAQ] : UART sample driver code for BF706mini
  • [FAQ] : “Peripherals view” in CCES
  • [FAQ]: Difference between Debug and Release configurations
  • [FAQ]: How to use "log10f_simd"
  • +µCOS-III Add-In: FAQ

FAQ: How do I instruct the compiler to generate SIMD code? It is not generated by default.

Question:

How do I instruct the compiler to generate SIMD code? It is not generated by default.

---------------------------------------------

Answer:

SIMD code is not generated by default for most SHARC processors for reasons that are explained below. The compiler supports a number of switches that allow you to control when SIMD code is generated. These switches are:

  • -loop-simd
    • Enables automatic use of SIMD mode in loops, aggregate assignments and inlined memcpy operations by asserting that data buffers are safe to access in this mode.
  • -asms-safe-in-simd-for-loops
    • Instructs the compiler that inline asm() statements inside loops marked with the SIMD_for pragma are safe to run unchanged in SIMD mode.
  • -linear-simd
    • Instructs the compiler to look for opportunities to use SIMD mode for parallel computations in linear code.
  • -no-linear-simd
    • Instructs the compiler not to use SIMD mode for parallel computations in linear code.
  • -no-simd
    • Disables all automatic use of SIMD mode.

 

On some SHARC processors, SIMD memory accesses to external memory are not possible, or may only be possible for certain memory types. Attempting to perform SIMD accesses to external memory on these processors can result in issues at run-time as data accesses using the 2nd processing element (“PEy”) will have no effect. In CrossCore Embedded Studio, the compiler’s behavior is conservative and it will not generate SIMD code if there is the possibility that SIMD accesses may fail. This restriction affects the following processors, for which SIMD code will not be generated by default:

  • ADSP-21160          // SIMD accesses to external memory may be affected by hardware anomalies
  • ADSP-21161          // SIMD accesses to external memory are not supported
  • ADSP-21367/8/9    // SIMD accesses to external memory are not supported
  • ADSP-21371/5       // SIMD accesses to external memory are not supported
  • ADSP-214xx          // SIMD accesses to external memory via the AMI bus are not supported

For the following processors, SIMD code is generated by default. These processors do not support direct access of external memory, so the limitations described above do not apply.

  • ADSP-2126x
  • ADSP-21363/4/5/6

Documentation

For more information on SIMD code generation, see the section “SIMD Support” in the C/C++ Compiler Manual.

Differences from VisualDSP++

In VisualDSP++, the compiler’s default behavior was to generate SIMD code, as long as certain criteria concerning alignment, aliasing and performance gains were met. If an application performed SIMD accesses, and the application used external memory, there was the potential for run-time errors that were difficult to diagnose. As described above, the compiler’s behavior in CrossCore Embedded Studio is now more conservative, which may result in out-of-the-box compiler performance appearing to be poorer. The switch “-loop-simd” can be used to reinstate the behavior of the VisualDSP++ compiler.

 

  • sharc
  • compiler
  • simd
  • Share
  • History
  • More
  • Cancel
Related
Recommended
Social
Quick Links
  • About ADI
  • ADI Signals+
  • Analog Dialogue
  • Careers
  • Contact us
  • Investor Relations
  • News Room
  • Quality & Reliability
  • Sales & Distribution
  • Incubators
Languages
  • English
  • 简体中文
  • 日本語
Newsletter

Interested in the latest news and articles about ADI products, design tools, training and events? Subscribe today!

Sign Up
Analog Logo
©1995 - 2023 Analog Devices, Inc. All Rights Reserved
沪ICP备09046653号-1
  • Sitemap
  • Legal
  • Privacy & Security
  • Privacy Settings
EngineerZone Uses cookies to ensure you get the best experience in our community. For more information on cookies, please read our Privacy & Security Statement.