What is the purpose of cache invalidation and cache flushing and also what happens if we don't take care of cache invalidation and cache flushing?
Flush operation makes the data in SDRAM same as Cache line, so that the DMA can access the newly core processed data.
If input data buffer resides in cacheable memory, then after modifying the buffer it should be flushed from memory using the flush_data_buffer.This prevents the DMA transfer from accessing stale data.
The FLUSH instruction causes the data cache to synchronize the specified cache-line with the external memory.
To know more about flush_data_buffer please refer the below CCES help path.
CrossCore® Embedded Studio <version> > System Run-Time Documentation > Cache and CPLBs > SHARC+ Caching Configuration and Support Functions > flush_data_buffer
Invalidate operation invalidates the existing cache line so that the new SDRAM data modified by DMA can be brought to the Cache line.
once DMA updates the buffer in memory, the stale copy in L1-cache must be invalidated. There are times when invalidation is required to clear the cache unconditionally and other times when the cache must be cleared while ensuring that any updated copy is not cleared without writing back to L2 or L3.
To know more about Cache Invalidation please refer the below CCES help path.
CrossCore® Embedded Studio <version> > System Run-Time Documentation > Cache and CPLBs > SHARC+ Caching Configuration and Support Functions > Cache Invalidation
By invalidating the cache-lines associated with the buffer, “coherency” is maintained between the contents stored in cache and the actual values in source memory.