Example project for ADSP-BF609 EZKIT which helps to understand EXTCLK mode in Timer using SSLDD APIs
This example demonstrates configuration of Gp timer 2 in EXTCLK mode and it will rise interrupt when counter register value meets programmed period register in timer2.
GP timer 1 is configured in PWM mode and generates signal in TM0_TMR1 pin (PWM) based on duty cycle which is connected to TM0_TMR2 pin (EXTCLK).
LED1(PG_14) is toggled in Timer Handler of Timer 2. Kindly find the attached image of period measurements for references.
For more information of application, please read "Readme_Timer_EXTCLK_.MODE.txt" file in the attached project.