In SPI while sending data from master to slave, how to deassert "Slave select" signal for a particular period of time during each frame transfer?
SPI_DLY_STOP bit provides exact delay in terms of SPI clock cycles between each SPI frames.
This is achieved with the help of calling adi_spi_SetSlaveSelectDelay()API in application when we set .
Deassertion of slave can be seen during delay between each SPI frames only if we control Slave select by hardware.
By calling adi_spi_SetHwSlaveSelect(handle,true) API, SPI hardware control the slave assertion and deassertion automatically.
In that attached Blackfin code, we run SPI nearly 1MHZ. Each clock cycle timing is 1μs. So we have to set nDelay cycles between slave as '3' in API like below for creating a delay of 3μs between each frames.
adi_spi_SetSlaveSelectDelay(handle,false,false,3);//delay-3 SPI clock cycles