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Interrupt Self-Nesting in CCES

According the page 4-35 of SHARCRegistered Processor Programming Reference (Includes ADSP-2136x, ADSP-2137x, and ADSP-214xx SHARC Processors Revision 2.2 March 2011) ADSP-21489 has Interrupt Self-Nesting.

Can I use it in C/C++ CCES?

For http://ez.analog.com/thread/19118 solution I can change super fast interrupt dispacther.

Example

I have the timecore interrupt with using the alternate (secondary) register set and interrupt nesting is disabled.

The timecore interrupt raise the software interrupt with using the main register set and interrupt nesting is enabled.

So I have OS which is free of charge.