Interrupt Self-Nesting in CCES

Question

According the page 4-35 of SHARC &#x00ae; Processor Programming Reference (Includes ADSP-2136x, ADSP-2137x, and ADSP-214xx SHARC Processors Revision 2.2 March 2011) ADSP-21489 has Interrupt Self-Nesting. 
 Can I use it in C/C++ CCES? 
 For https://ez.analog.com/thread/19118 solution I can change super fast interrupt dispacther. 
 Example 
 I have the timecore interrupt with using the alternate (secondary) register set and interrupt nesting is disabled . 
 The timecore interrupt raise the software interrupt with using the main register set and interrupt nesting is enabled. 
 So I have OS which is free of charge.

JamesH · Accepted Answer

Hi, One possible way to avoid this situation is to use a lower-priority interrupt level to act as an intermediate interrupt. For example, you could use software interrupt SFT2I for the actual work of your interrupt, then you could use SFT3I as an intermediate interrupt that simply raises SFT2I. So, here’s how it would look: Timer Interrupt (handler): BIT SET IRPTL SFT3I; SFT2I Interrupt (handler): SFT3I Interrupt (app_IVT.asm hardware vector code): .RETAIN_NAME ___int_SFT3I; ___int_SFT3I: RTI (DB); // Just return… BIT SET IRPTL SFT2I; // …setting SFT2I before you go. NOP; // 2nd delay slot NOP; // unused .___int_SFT3I.end: The SHARC hardware only clears the latch bit for the currently executing interrupt. If you use SFT3I as the intermediate interrupt, then it will be possible for the Timer Interrupt to raise SFT3I whilst SFT2I is currently executing. By doing this you should not lose an interrupt in the way that you describe. We have encountered the same issue before on VDK (in VisualDSP) on SHARC, and we used the above SFT3I interrupt “trampoline” as a solution. Please let us know if this helps. Thanks JamesH)

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Interrupt Self-Nesting in CCES